SCAN18373T Просмотр технического описания (PDF) - Fairchild Semiconductor

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SCAN18373T

Transparent Latch with 3-STATE Outputs

Fairchild Semiconductor 

Description of Boundary-Scan Circuitry

The scan cells used in the BOUNDARY-SCAN register are

one of the following two types depending upon their loca-

tion. Scan cell TYPE1 is intended to solely observe system

data, while TYPE2 has the additional ability to control sys-

tem data.

Scan cell TYPE1 is located on each system input pin while

scan cell TYPE2 is located at each system output pin as

well as at each of the two internal active-high output enable

signals. AOE controls the activity of the A-outputs while

BOE controls the activity of the B-outputs. Each will acti-

vate their respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage

identical to scan cell TYPE1. It captures a fixed logic low.

to the SCAN18373T device. SCAN CMOS Test Access

Logic devices do not include the IEEE 1149.1 optional

identification register. Therefore, this unique captured

value can be used as a “pseudo ID” code to confirm that

the correct device is placed in the appropriate location in

the boundary scan chain.

Instruction Register Scan Chain Definition

Bypass Register Scan Chain Definition Logic 0

The INSTRUCTION register is an eight-bit register which

captures the value 00111101.

The two least significant bits of this captured value (01) are

required by IEEE Std 1149.1. The upper six bits are unique

MSB → LSB

Instruction Code

00000000

10000001

10000010

00000011

All Others

Instruction

EXTEST

SAMPLE/PRELOAD

CLAMP

HIGHZ

BYPASS

Scan Cell TYPE1

Scan Cell TYPE2

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