M80C186EB Просмотр технического описания (PDF) - Intel

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производитель

M80C186EB

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

Intel 

M80C186EB

Name

S2 0

ALE

BHE

RD

WR

READY

DEN

DT R

LOCK

Table 4 M80C186EB Pin Descriptions (Continued)

Type

Description

O

H(Z)

R(Z)

P(1)

Bus cycle Status are encoded on these pins to provide bus transaction

information S2 0 are encoded as follows

S2 S1 S0 Bus Cycle Initiated

0 0 0 Interrupt Acknowledge

0 0 1 Read I O

0 1 0 Write I O

0 1 1 Processor HALT

1 0 0 Queue Instruction Fetch

1 0 1 Read Memory

1 1 0 Write Memory

1 1 1 Passive (no bus activity)

O

Address Latch Enable output is used to strobe address information into a

H(0)

transparent type latch during the address phase of the bus cycle

R(0)

P(0)

O

H(Z)

R(Z)

P(X)

Byte High Enable output to indicate that the bus cycle in progress is

transferring data over the upper half of the data bus BHE and A0 have the

following logical encoding

A0 BHE Encoding

00

Word Transfer

01

Even Byte Transfer

10

Odd Byte Transfer

11

Refresh Operation

O

H(Z)

R(Z)

P(1)

ReaD output signals that the accessed memory or I O device must drive

data information onto the data bus

O

H(Z)

R(Z)

P(1)

WRite output signals that data available on the data bus are to be written

into the accessed memory or I O device

I

READY input to signal the completion of a bus cycle READY must be

A(L)

active to terminate any M80C186EB bus cycle unless it is ignored by

S(L)

correctly programming the Chip-Select Unit

O

H(Z)

R(Z)

P(1)

Data ENable output to control the enable of bi-directional transceivers

when buffering a M80C186EB system DEN is active only when data is to be

transferred on the bus

O

H(Z)

R(Z)

P(X)

Data Transmit Receive output controls the direction of a bi-directional

buffer when buffering an M80C186EB system

IO

H(Z)

R(WH)

P(1)

LOCK output indicates that the bus cycle in progress is not to be

interrupted The M80C186EB will not service other bus requests (such as

HOLD) while LOCK is active This pin is configured as a weakly held high

input while RESIN is active and must not be driven low

16

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