M80C186EB Просмотр технического описания (PDF) - Intel

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M80C186EB

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

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M80C186EB

M80C186EB Peripheral Architecture

The M80C186EB has integrated several common

system peripherals with a CPU core to create a com-

pact yet powerful system The integrated peripher-

als are designed to be flexible and provide logical

interconnections between supporting units (e g the

interrupt control unit supports interrupt requests

from the timer counters or serial channels)

The list of integrated peripherals include

 7-Input Interrupt Control Unit

 3-Channel Timer Counter Unit

 2-Channel Serial Communications Unit

 10-Output Chip-Select Unit

 I O Port Unit

 Refresh Control Unit

 Power Management Unit

The registers associated with each integrated peri-

heral are contained within a 128 x 16 register file

called the Peripheral Control Block (PCB) The PCB

can be located in either memory or I O space on

any 256 Byte address boundary During bus cycles

that access the PCB the bus controller will signal

the operation externally (i e the RD WR status

address data etc lines will be driven as in a normal

bus cycle) However READY is ignored and the con-

tents of the data bus during a read operation is ig-

nored

The starting address of the PCB is controlled by a

relocation register and can overlap any of the mem-

ory or I O regions programmed into the Chip Select

Unit In this case the overlapped chip select will not

go active when the PCB is read or written

Figure 6 provides a list of the registers associated

with the PCB The Register Bit Summary at the end

of this specification individually lists all of the regis-

ters and identifies each of their programming attri-

butes

INTERRUPT CONTROL UNIT

The M80C186EB can receive interrupts from a num-

ber of sources both internal and external The inter-

rupt control unit serves to merge these requests on

a priority basis for individual service by the CPU

Each interrupt source can be independently masked

by the Interrupt Control Unit (ICU) or all interrupts

can be globally masked by the CPU

Internal interrupt sources include the Timers and Se-

rial channel 0 External interrupt sources come from

the five input pins INT4 0 The NMI interrupt pin is

not controlled by the ICU and is passed directly to

the CPU Although the Timer and Serial channel

each have only one request input to the ICU sepa-

rate vector types are generated to service individual

interrupts within the Timer and Serial channel units

The M80C186EB ICU provides a mechanism for ex-

panding the number of external interrupt sources

Two pairs of pins can be independently configured

to support an external slave interrupt controller

(82C59A) Each pair of external pins can be expand-

ed to support 64 interrupts making it possible for the

M80C186EB to support a total of 129 external inter-

rupts

The ICU may be used in a polled mode if interrupts

are undesirable When polling the processor dis-

ables interrupts and then polls the ICU whenever it is

convenient

TIMER COUNTER UNIT

The M80C186EB Timer Counter Unit (TCU) pro-

vides three 16-bit programmable timers Two of

these are highly flexible and are connected to exter-

nal pins for control or clocking A third timer is not

connected to any external pins and can only be

clocked internally However it can be used to clock

the other two timer channels The TCU can be used

to count external events time external events gen-

erate non-repetitive waveforms generate timed in-

terrupts etc

Each timer has at least one 16-bit compare register

and one 16-bit count register Timers 0 and 1 each

have an additional 16-bit compare register The

count register is incremented every fourth CPU clock

cycle (internal clocking) every time Timer2 expires

(Timers 0 and 1 only) or every Low-to-High tran-

sition on the timer input pin (Timers 0 and 1 only)

The input clock to Timers 0 and 1 must not exceed

one fourth the operating frequency of the

M80C186EB When the count register matches the

value programmed into the compare register sever-

al operations may happen

All three timers can generate an interrupt when the

compare register matches the value in the count

register Additionally Timers 0 and 1 have an output

pin that can change state or pulse when the com-

pare condition occurs

10

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