MT93L16 Просмотр технического описания (PDF) - Mitel Networks

Номер в каталоге

Компоненты Описание

производитель

MT93L16

Low-Voltage Acoustic Echo Canceller

Mitel Networks 

Preliminary Information

MT93L16

Pin Description (continued)

Pin # Name

Description

14 RESET Reset / Power-down (Input). An active low resets the device and puts the MT93L16 into a

low-power stand-by mode.

15, 16 NC No Connect (Output). These pins should be left un-connected.

17

SCLK Serial Port Synchronous Clock (Input). Data clock for the serial microport interface.

18

CS Serial Port Chip Select (Input). Enables serial microport interface data transfers. Active low.

19 DATA2 Serial Data Receive (Input). In Motorola/National serial microport operation, the DATA2 pin

is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and

must be tied to Vss or Vdd.

20 DATA1 Serial Data Port (Bidirectional). In Motorola/National serial microport operation, the DATA1

pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for

transmitting and receiving data.

21

NC No Connect (Output). This pin should be left un-connected.

22

VDD Positive Power Supply (Input). Nominally 3.3 volts.

23

Sout Send PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.

Data may be in either companded or 2’s complement linear PCM format. This is the Send

Out signal after acoustic echo cancellation and non-linear processing. Data bits are clocked

out following SSI, ST-BUS, or GCI timing requirements.

24

Rout Receive PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.

Data may be in either companded or 2’s complement linear PCM format. This is the Receive

out signal after line echo cancellation non-linear processing, AGC, and gain control. Data bits

are clocked out following SSI, ST-BUS, or GCI timing requirements.

25

F0i Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low (or active-high)

frame alignment pulse, respectively. SSI operation is enabled by connecting this pin to Vss.

26 BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit

clock. This clock must be synchronous with ENA1, and ENA2 enable strobes.

In ST-BUS or GCI operation, C4i pin must be connected to the 4.096MHz (C4) system clock.

27, 28

IC Internal Connection (Input). Tie to Vss.

29

VSS2 Digital Ground (Input): Nominally 0 volts.

30

VDD2 Positive Power Supply (Input): Nominally 3.3 volts (tie together with VDD, pin 22).

31

VSS Digital Ground (Input): Nominally 0 volts (tie together with VSS2, pin 29).

32

NC No Connect (Output). This pin should be left un-connected.

33 MCLK2 Master Clock (Input): Nominal 20MHz master clock (tie together with MCLK, pin 8).

34,35,36 IC Internal Connection (Input). Tie to Vss.

Notes: 1. All inputs have CMOS compatible, 5V-tolerant logic levels.

2. All outputs have CMOS logic levels. Rout, Sout, and DATA1 are 5V-tolerant when tristated (to withstand other 5V drivers

on a shared bus).

Glossary

Double-Talk

Near-end Single-Talk

Far-end Single-Talk

ADV NLP

Howling

Narrowband

NBSD

Noise-Gating

Offset Nulling

Reverberation time

ERL

ERLE

AGC

Simultaneous signals present on Rin and Sin.

Signals only present at Sin input.

Signals only present at Rin input.

Advanced Non-Linear-Processor

Oscillation caused by feedback from acoustic and line echo paths

Any mono or dual sinusoidal signals

Narrow Band Signal Detector

Audible switching of background noise

Removal of DC component

The time duration before an echo level decays to -60dBm

Echo Return Loss

Echo Return Loss Enhancement

Automatic Gain Control

3

Share Link: