PFM19030 Просмотр технического описания (PDF) - Cree, Inc
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PFM19030 Datasheet PDF : 15 Pages
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Electrical Specification (Continued)
PFM19030
MAXIMUM RATINGS
Rating
DC Drain Supply
19
a) Drain-to-Source Voltage, (VGS=0), D1 & D2
& Track D1 & Track D2
b) Normal Operation (Class AB operation)
DC Gate Supply
20
a) Gate-to-source Voltage (VDS=0)
Normal Operation (Class AB operation)
21 RF Input Power
Maximum Power Dissipation (T ≤ +85 °C)
22
a) Derate above +85 °C base temperature.
23 Maximum Channel Operating Temperature
24 Storage Temperature Range
Symbol
VDS
VD_SUPPLY
VGS
VG_SUPPLY
PIN
PTOTAL
TCH
TSTG
Value
+50
+30
-0.5<VGS<+15
0<VGS<+6
+25
65
-0.7
+200
-40 to +150
Units
Volts DC
Volts DC
Volts DC
Volts DC
dBm
Watts
Watts/°C
°C
°C
RECOMMENDED SOURCE AND LOAD IMPEDANCES
Impedance Units
Comments
Nominal Source
Impedance for
Optimum Operation
Nominal Load
Impedance for
Optimum Operation
19 + j1.9
21 + j6.3
Ohms
Ohms
Matched for near-optimum linearity and gain flatness.
Impedance is looking from the module input lead into the
input matching circuit. Reference plane is 0.105 inches from
the input end (case edge)of the module.
Matched for near-optimum linearity under CDMA protocol.
Impedance is from the module output lead looking into the
output matching circuit. Reference plane is 0.105 inches from
the output end (case edge) of the module.
Specification Notes:
1) The module is mounted in a test fixture with external matching elements for all testing. Quiescent current bias
conditions are those appropriate for minimum ACPR under CDMA protocol. Supply voltage for all tests is
+27 volts DC. Testing is at +25 °C unless otherwise specified.
2) Theta jc is measured with a package mounting (base) temp of +85 °C, and with 10 Watts CW output.
3) Pout=5Watts average; IS-95A protocol: IS95 Forward Link PPS+ 9CH.
ACPR conditions: a) 900 kHz offset, 30 kHz BW, b) 2.75 MHz offset, 1 MHz BW.
4) Sense FETs are scaled versions of the main RF FETs, formed from electrically isolated cells at end of the RF
structure. Current scales according to periphery (threshold voltages offset is less than ±150 millivolts between
adjacent devices). RF & Sense FET gates and sources are DC connected. Drains are DC isolated. Leads S1 & S2
are DC connected to drains of sense FETs 1 & 2. Sources are connected to package base. Sense FETs are
electrically isolated from the RF signals.
Page 3 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 2
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