PDSP16318 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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PDSP16318 Datasheet PDF : 8 Pages
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PDSP16318 MC
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
Tamb (Military) =-55°C to +125°C, VCC = 5.0V ± 10%, GND = 0V
STATIC CHARACTERISTICS
Characteristic
Symbol
Min.
Value
Typ.
Units Sub
Max.
group
Conditions
* Output high voltage
V
OH
* Output low voltage
VOL
* Input high voltage
VIH
* Input low voltage
V
IL
V
IH
* Input leakage current
VI IL
IL
* Output leakage current
loz
† Output SC current
IOS
† Input capacitance
C
IN
SWITCHING CHARACTERISTICS
2.4
-
2.0
-
Vdd - 1
-
-10
-50
20
-
Characteristic
* Clock period
† Clock High Time
† Clock Low Time
† A15:0, B15:0 setup to clock rising edge
† A15:0, B15:0 hold after clock rising edge
† MS, S2:0, ASI setup to clock rising edge
† DEL, ASR, CLR setup to clock rising edge
† DEL, ASR, CLR, MS, S2:0, ASI hold after
clock rising edge
† CEA, CEB setup to clock falling edge
† CEA, CEB hold after clock falling edge
† Clock rising edge to OVR, C15:0, D15:0
† OEC/OED low to C15:0/D15:0 high data valid
† OEC/OED low to C15:0/D15:0 low data valid
† OEC/OED high to C15:0/D15:0 high impedance
† Vcc current
-
V 1, 2, 3 IOH = 3.2mA
0.4
V 1, 2, 3 lOL=-3.2mA
-
V 1, 2, 3
0.8
V 1, 2, 3
-
V 1, 2, 3 CLK, CEA, CEB, OEC, OED
0.5
V 1, 2, 3 CLK, CEA, CEB, OEC, OED
+10
µA
1, 2, 3
GND < V <V
IN CC
-
+50
µA 1, 2, 3 GND <VIN < VCC
-
200
mA
Vcc = Max
9
-
pF
Value
Military
PDSP16318
Min. Max.
Units
100 -
ns
20
-
ns
20
-
ns
8
-
ns
2
-
ns
10
-
ns
8
-
ns
2
-
ns
2
-
ns
8
-
ns
5
40
ns
-
40
ns
-
40
ns
-
40
ns
-
70
mA
Sub
group
9, 10, 11
Conditions
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
VCC = max,
TTL input levels
Outputs unloaded,
fCLK = max
† Vcc current
-
30
mA
All parameters marked * are tested during production.
All parameters marked † are guaranteed by design and characterisation.
NOTES
1. LSTTL is equivalent to IOH = 20 microamps, IOL = -0.4mA
2. Current is defined as negative into the device
3. CMOS input levels are defined as:
V = 0.5V
IL
VIH = VDD - 0.5V
VCC = max,
CMOS input levels
Outputs unloaded,
fCLK = max
6
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