PDSP16318 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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производитель
PDSP16318 Datasheet PDF : 8 Pages
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PDSP16318 MC
Symbol
A15:0
B15:0
C15:0
D15:0
CLK
CEA
CEB
OEC
OED
OVR
ASR1:0
ASI1:0
CLR
MS
S2:0
DEL
VCC
GND
Type
Input
Input
Output
Output
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Power
Ground
Description
Data presented to this input is loaded into the input register on the rising edge of CLK. A15 is the MSB.
Data presented to this input is loaded into the input register on the rising edge of CLK. B15 is the MSB
and has the same weighting as A15.
New data appears on this output after the rising edge of CLK. C15 is the MSB.
New data appears on this output after the rising edge of CLK. D15 is the MSB.
Common Clock to all internal registers
Clock enable: when low the clock to the A input register is enabled.
Clock enable: when low the clock to the B input register is enabled.
Output enable: Asynchronous 3-state output control: The C outputs are in a high impedance
state when this input is high.
Output enable: Asynchronous 3-state output control: The D outputs are in a high impedance
state when this input is high.
Overflow flag: This flag will go high in any cycle during which either the output data overflows the number
range selected or either of the adder results overflow. A new OVR appears after the rising edge of the
CLK.
Add/subtract Real: Control input for the 'Real' adder. This input is latched by the rising edge of clock.
Add/subtract Imag: Control input for the 'Imag' adder. This input is latched by the rising edge of clock.
Accumulator Clear: Common accumulator clear for both Adder/Subtractor units. This input is latched by
the rising edge of CLK.
Mux select: Control input for both adder multiplexers. This input is latched by the rising edge of CLK.
When high the feedback path is selected.
Scaling control: This input selects the 16-bit field from the 20-bit adder result that is routed to the outputs.
This input is latched by the rising edge of CLK.
Delay Control: This input selects the delayed input to the real adder for operations involving the
PDSP16112. This input is latched by the rising edge of CLK.
+5V supply: Both Vcc pins must be connected.
0V supply: Both GND pins must be connected.
GG pin Function GG pin Function GG pin Function GG pin Function
77
D7
6
C7
31
A1
56
B10
82
D8
7
C6
32
A2
57
B9
83
D9
8
C5
33
A3
58
B8
84
D10
9
C4
34
A4
59
B7
85
GND
10
C3
35
A5
60
B6
86
VCC
11
C2
36
A6
61
B5
87
D11
12
C1
37
A7
62
B4
88
D12
13
C0
38
A8
63
B3
89
D13
14
OED
39
A9
64
B2
90
D14
15
OEC
40
A10
65
B1
91
D15
16
S2
41
A11
66
B0
92
C15
17
S1
42
A12
67
CLK
93
C14
18
94
C13
19
S0
43
A13
68
CEB
MS
44
A14
69
OVR
95
C12
20
ASI1
45
A15
70
D0
96
VCC
21
ASI0
46
CEA
71
D1
97
GND
22
DEL
47
B15
72
D2
98
C11
23
CLR
48
B14
73
D3
99
C10
24
ASR1
49
B13
74
D4
100
C9
25
ASR0
50
B12
75
D5
5
C8
26
A0
51
B11
76
D6
Device Pinout for ceramic QFP (GC100)
3
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