PDSP16318 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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PDSP16318 Datasheet PDF : 8 Pages
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PDSP16318 MC
PDSP16318 MC
Complex Accumulator
DS3761
ISSUE 2.1
November 1998
The PDSP16318 contains two independent 20-bit Adder/
Subtractors combined with accumulator registers and shift
structures. The four port architecture permits full 10MHz
throughout in FFT and filter applications.
Two PDSP16318s combined with a single PDSP16112A
Complex Multiplier provide a complete arithmetic solution for
a Radix 2 DIT FFT Butterfly. A new complex Butterfly result
can be generated every 100ns allowing 1k complex FTT's to
to be executed in 512µs.
FEATURES
s Full 10MHz Throughout in FFT Applications
s Four Independent 16-bit I/O Ports
s 20-bit Addition or Accumulation
s Fully Compatible with PDSP16112 Complex Multiplier
s On Chip Shift Structures for Result Scaling
s Overflow Detection
s Independent Three-State Outputs and Clock
Enables for 2 Port 10MHz Operation
s 1.4 micron CMOS
s 500mW Maximum Power Dissipation
s 100 pin ceramic QFP
ORDERING INFORMATION
PDSP16318/MC/GC1R (Ceramic QFP Package -
MIL STD 883 Screening)
GC100
Fig.1 Pin connections
Rev
A
B
C
D
Date
MAR 1993 NOV 1998
NOTE
Polyimide is used as an inter-layer dielectric and as
glassivation.
A
REG
DELAY
B
SHIFT
REG
C
A
B
REG
A
SHIFT
REG
D
B
Fig.2 PDSP16318 simplified block diagram
1
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