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OR2C04A

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

ORCA Series 2 FPGAs

Data Sheet

January 2002

FPGA Configuration Modes (continued)

Slave Serial Mode

The slave serial mode is primarily used when multiple

FPGAs are configured in a daisy chain. The serial slave

serial mode is also used on the FPGA evaluation board

which interfaces to the download cable. A device in the

slave serial mode can be used as the lead device in a

daisy chain. Figure 44 shows the connections for the

slave serial configuration mode.

The configuration data is provided into the FPGA’s DIN

input synchronous with the configuration clock CCLK

input. After the FPGA has loaded its configuration data,

it retransmits the incoming configuration data on

DOUT. CCLK is routed into all slave serial mode

devices in parallel.

Multiple slave FPGAs can be loaded with identical con-

figurations simultaneously. This is done by loading the

configuration data into the DIN inputs in parallel.

DOUT

TO DAISY-

CHAINED

DEVICES

MICRO-

PROCESSOR

OR

DOWNLOAD

CABLE

INIT

PRGM

DONE

CCLK

DIN

ORCA

SERIES

FPGA

VDD

M2

M1

M0

HDC

LDC

5-4485(F)

Figure 44. Slave Serial Configuration Schematic

Slave Parallel Mode

The slave parallel mode is essentially the same as the

slave serial mode except that 8 bits of data are input on

pins D[7:0] for each CCLK cycle. Due to 8 bits of data

being input per CCLK cycle, the DOUT pin does not

contain a valid bit stream for slave parallel mode. As a

result, the lead device cannot be used in the slave

parallel mode in a daisy-chain configuration.

Figure 45 is a schematic of the connections for the

slave parallel configuration mode. WR and CS0 are

active-low chip select signals, and CS1 is an active-

high chip select signal. These chip selects allow the

user to configure multiple FPGAs in slave parallel

mode using an 8-bit data bus common to all of the

FPGAs. These chip selects can then be used to select

the FPGA(s) to be configured with a given bit stream,

but once an FPGA has been selected, it cannot be

deselected until it has been completely programmed.

8

MICRO-

PROCESSOR

OR

VDD

SYSTEM

D[7:0]

DONE

INIT

CCLK

PRGM

ORCA

SERIES

FPGA

CS1

CS0

WR

M2

HDC

M1

LDC

M0

5-4487(F)

Figure 45. Slave Parallel Configuration Schematic

50

Lattice Semiconductor

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