OR2C04A Просмотр технического описания (PDF) - Lattice Semiconductor
Номер в каталоге
Компоненты Описание
производитель
OR2C04A Datasheet PDF : 192 Pages
| |||
ORCA Series 2 FPGAs
Data Sheet
January 2002
Configuration Data Format (continued)
Table 9. Configuration Frame Format and Contents
Header
ID Frame
(Optional)
Configuration
Data
Frame
(repeated for
each data frame)
End of
Configuration
Postamble
11111111
0010
24-Bit Length Count
1111
0
P—1
C—0
Opar, Epar
Addr[10:0] =
11111111111
Prty_En
Reserved [42:0]
ID
111
0
P—1 or 0
C—1 or 0
Opar, Epar
Addr[10:0]
A
1
Data Bits
.
.
111
0010011111111111
111111 . . . . .
Leading header—4 bits minimum dummy bits
Preamble
Configuration frame length
Trailing header—4 bits minimum dummy bits
Frame start
Must be set to 1 to indicate data frame
Must be set to 0 to indicate uncompressed
Frame parity bits
ID frame address
Set to 1 to enable parity
Reserved bits set to 0
20-bit part ID
Three or more stop bits (high) to separate frames
Frame start
1 indicates data frame; 0 indicates all frames are written
Uncompressed—0 indicates data and address are supplied;
Compressed—1 indicates only address is supplied
Frame parity bits
Column address in FPGA to be written
Alignment bit (different number of 0s needed for each part)
Write bit—used in uncompressed data frame
Needed only in an uncompressed data frame
.
.
One or more stop bits (high) to separate frames
16 bits—00 indicates all frames are written
Additional 1s
Note:
For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must
be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive
integer. The number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. Note also that the bit
stream generator tool supplies a bit stream which is compatible with all configuration modes, including slave parallel mode.
46
Lattice Semiconductor
Share Link: 