NE570D(2003) Просмотр технического описания (PDF) - Philips Electronics
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NE570D Datasheet PDF : 12 Pages
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Philips Semiconductors
Compandor
Product data
NE570
CIRCUIT DESCRIPTION
The NE570 compandor building blocks, as shown in the block
diagram, are a full-wave rectifier, a variable gain cell, an operational
amplifier and a bias system. The arrangement of these blocks in the
IC result in a circuit which can perform well with few external
components, yet can be adapted to many diverse applications.
The full-wave rectifier rectifies the input current which flows from the
rectifier input, to an internal summing node which is biased at VREF.
The rectified current is averaged on an external filter capacitor tied
to the CRECT terminal, and the average value of the input current
controls the gain of the variable gain cell. The gain will thus be
proportional to the average value of the input signal for
capacitively-coupled voltage inputs as shown in the following
equation. Note that for capacitively-coupled inputs there is no offset
voltage capable of producing a gain error. The only error will come
from the bias current of the rectifier (supplied internally) which is
less than 0.1 µA.
G
T
|VIN * VREF
R1
|
avg
or
G
T
|
VIN | avg
R1
The speed with which gain changes to follow changes in input signal
levels is determined by the rectifier filter capacitor. A small capacitor
will yield rapid response but will not fully filter low frequency signals.
Any ripple on the gain control signal will modulate the signal passing
through the variable gain cell. In an expander or compressor
application, this would lead to third harmonic distortion, so there is a
trade-off to be made between fast attack and decay times and
distortion. For step changes in amplitude, the change in gain with
time is shown by this equation.
G(t) + (Ginitial * Gfinal)e * tńt ) Gfinal ; t + 10k CRECT
The variable gain cell is a current-in, current-out device with the ratio
IOUT/IIN controlled by the rectifier. IIN is the current which flows from
the ∆G input to an internal summing node biased at VREF. The
following equation applies for capacitively-coupled inputs. The
output current, IOUT, is fed to the summing node of the op amp.
IIN
+
VIN * VREF
R2
+
VIN
R2
A compensation scheme built into the ∆G cell compensates for
temperature and cancels out odd harmonic distortion. The only
distortion which remains is even harmonics, and they exist only
because of internal offset voltages. The THD trim terminal provides
a means for nulling the internal offsets for low distortion operation.
The operational amplifier (which is internally compensated) has the
non-inverting input tied to VREF, and the inverting input connected to
the ∆G cell output as well as brought out externally. A resistor, R3, is
brought out from the summing node and allows compressor or
expander gain to be determined only by internal components.
The output stage is capable of ±20 mA output current. This allows a
+13 dBm (3.5 VRMS) output into a 300 Ω load which, with a series
resistor and proper transformer, can result in +13 dBm with a 600 Ω
output impedance.
A bandgap reference provides the reference voltage for all summing
nodes, a regulated supply voltage for the rectifier and ∆G cell, and a
bias current for the ∆G cell. The low tempco of this type of reference
provides very stable biasing over a wide temperature range.
The typical performance characteristics illustration shows the basic
input-output transfer curve for basic compressor or expander
circuits.
+20
+10
0
–10
–20
–30
–40
–50
–60
–70
–80
–40 –30 –20 –10 0 +10
COMPRESSOR OUTPUT LEVEL
OR
EXPANDOR INPUT LEVEL (dBm)
SR00677
Figure 3. Basic input-output transfer curve
TYPICAL TEST CIRCUIT
VCC = 15 V
0.1 µF
13
3, 14 20 kΩ
V1
∆G
2.2 µF
10 µF
20 kΩ
–
+
6, 11
7, 10
VO
2, 15
V2
2.2 µF
10 kΩ
VREF
30 kΩ
4
1, 16
5, 12
8, 9
2.2 µF 8.2 kΩ
200 pF
Figure 4. Typical Test Circuit
SR02508
2003 Apr 03
4
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