MX86250 Просмотр технического описания (PDF) - Macronix International

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MX86250

THE ADVANCED 64-BIT WINDOWS-95 AND DIRECTDRAW ACCELERATOR

Macronix International 

INDEX

MX86250

PCI Bus Interface Pins:(continued)

Pin Name

PAR

INTRB

IDSEL

CBE0#

CBE1#

CBE2#

CBE3#

Pin No. Type Description

174 TO This output is PAR. It is only driven during PCI bus master doing read accesses

from GUI. When driven, it will provide an even parity across the AD[31:0], and

C/BE#[3:0]. This signal is an tri-state output.

168 TO This output is INTA#. It is and interrupt request signal to system interrupt

controller. This signal always hard wired to the PCI bus INTA# signal pin. It is an

open drained output. This pin is typically unused in display subsystem design, but

may be connected to IRQ9 via PCI configuration register.

181 I

This input is IDSEL. It is used as an Initialization Device Select during PCI bus

Auto-configuration cycles. When high, it indicates that GUI is now selected as a

target for PCI bus configuration cycles.

180 I

This multiplexed input is part of a PCI bus Command definition or a Byte Enable for

byte lane 0. During address phase of a PCI bus transaction, it defines the

Command. During data phase of a PCI bus transaction, it defines if byte lane 0 is

engaged in the transfer or not.

179 I

This is bit 1 of bus command and byte enable.

177 I

This is bit 2 of bus command and byte enable.

175 I

This is bit 3 of bus command and byte enable.

The PCI bus Commands supported are listed below:

C\BE[3:0]#

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1010

1100

1101

1110

PCI bus Command Type

(Interrupt Acknowledge)

(Special Cycle)

I/O Read

I/O Write

reserved

reserved

Memory Read

Memory Write

reserved

reserved

Configuration Read

Configuration Write

Memory Read Multiple

(Dual Address Cycle)

Memory Read Line

1111

Memory Write and Invalidate

P/N:PM0387

REV. 1.1, JUL 26, 1996

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