MX25L12805D Просмотр технического описания (PDF) - Unspecified

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производитель

MX25L12805D

128M-BIT [x 1] CMOS SERIAL FLASH

Unspecified 

MX25L12805D

Table 1. Protected Area Sizes

Status bit

BP3 BP2 BP1 BP0

11

1

1

11

1

0

11

0

1

11

0

0

10

1

1

10

1

0

10

0

1

10

0

0

01

1

1

01

1

0

01

0

1

01

0

0

00

1

1

00

1

0

00

0

1

00

0

0

Protection Area

128Mb

All

All

All

All

All

All

All

Upper half (hundrend and twenty-eight sectors: 128 to 255)

Upper quarter (sixty-four sectors: 192 to 255)

Upper eighth (thirty-two sectors: 224 to 255)

Upper sixteenth (sixteen sectors: 240 to 255)

Upper 32nd (eight sectors: 248 to 255)

Upper 64th (four sectors: 252 to 255)

Upper 128th (two sectors: 254 and 255)

Upper 256th (one sector: 255)

None

Note:

1. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.

P/N: PM1310

REV. 1.1, OCT. 01, 2008

7

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