MX25L4005M2I-15 Просмотр технического описания (PDF) - Macronix International

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MX25L4005M2I-15

4M-BIT [x 1] CMOS SERIAL FLASH

Macronix International 

MX25L4005

DATA PROTECTION

The MX25L4005 is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power

transition. During power up the device automatically resets

the state machine in the Read mode. In addition, with its

control register architecture, alteration of the memory

contents only occurs after successful completion of

specific command sequences. The device also

incorporates several features to prevent inadvertent write

cycles resulting from VCC power-up and power-down

transition or system noise.

• Power-On Reset and an internal timer (tPUW) can

provide protection against inadvertant changes while

the power supply is outside the operating specification.

• Program, Erase and Write Status Register instructions

are checked that they consist of a number of clock

pulses that is a multiple of eight, before they are

accepted for execution.

• All instructions that modify data must be preceded by

a Write Enable (WREN) instruction to set the Write

Enable Latch (WEL) bit . This bit is returned to its reset

state by the following events:

- Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

• The Block Protect (BP2, BP1, BP0) bits allow part of

the memory to be configured as readonly. This is the

Software Protected Mode (SPM).

• The Write Protect (WP#) signal allows the Block

Protect (BP2, BP1, BP0) bits and Status Register

Write Disable (SRWD) bit to be protected. This is the

Hardware Protected Mode (HPM).

• In addition to the low power consumption feature, the

Deep Power-down mode offers extra software protec-

tion from inadvertent Write, Program and Erase in-

structions, as all instructions are ignored except one

particular instruction (the Release from Deep

Powerdown instruction).

• To avoid unexpected changes by system power supply

transition, the Power-On Reset and an internal timer

(tPUW) can protect the device.

• Before the Program, Erase, and Write Status Register

execution, instruction length will be checked on follow-

ing the clock pulse number to be multiple of eight base.

• Write Enable (WREN) instruction must set to Write

Enable Latch (WEL) bit before writing other instructions

to modify data. The WEL bit will return to reset state by

following situations:

- Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

• The Software Protected Mode (SPM) use (BP2, BP1,

BP0) bits to allow part of memory to be protected as

read only.

• The Hardware Protected Mode (HPM) use WP# to

protect the (BP2, BP1, BP0) bits and SRWD bit.

• Deep-Power Down Mode also protects the device by

ignoring all instructions except Release from Deep-

Power Down (RDP) instruction and RES instruction.

P/N: PM1236

REV. 1.1, SEP. 30, 2005

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