MV8870 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MV8870 Datasheet PDF : 12 Pages
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MV8870/MV8870-1
PIN DESCRIPTIONS (Note 1)
Symbol Pin no
IN+,
1 (1)
IN -
2 (2)
GS
3 (3)
VREF 4 (5)
SEL
5 (7)
PD
6 (10)
FHT
FH
OSC1
- (8)
- (9)
7 (12)
OSC2 8 (13)
VSS
TOE
9 (14)
10 (16)
Q1
11 (17)
Q2
12 (18)
Q3
13 (19)
Q4
14 (20)
FL
- (21)
FLT
- (22)
StD
15 (25)
ESt
16 (26)
SVGT 17 (27)
VDD
18 (28)
Pin name and description
In Plus and Minus (Voltage Inputs). These are respectively the non-inverting and inverting
inputs to the front-end op-amp. The DTMF input is applied to these pins in normal operation.
Gain Select (Voltage Output). This pin is connected to the output of the front-end op-amp. A
feedback resistor between this pin and the inverting input (IN - ) controls the front-end gain.
Reference Voltage (Voltage Output). This pin outputs a voltage which is half-way between the
power supply voltages (VSS and VDD). It can be used to bias the input signal.
Select Input. This pin determines the Q4........Q1 truth table as shown in Fig. 6
Power Down Input. This pin is used to power down and inhibit the oscillator. It is active high
and includes an internal pull-up resistor.
Fllter High Tones. Sine wave output from the high group filter circuit.
High Frequency OutpuL Square wave output from the high group zero crossing detector.
Oscillator 1 (Digltal Input). This is the input to the inverter of the oscillator circuit. There is an
internal biasing resistor between this pin and the inverter output (OSC2). A 3.579545MHz crystal
is normally connected externally between the two pins to complete the oscillator circuit.
Oscillator 2 (Digital Output). This is the output of the inverter of the oscillator circuit. There is an
internal biasing resistor between this pin and the inverter input (OSC1). A 3.579545MHz crystal is
normally connected externally between the two pins to complete the oscillator circuit.
Negative Supply (Power Input). This is the negative power supply for the device. It is
normally 0V.
Three-State Output Enable (Digital Input with Pull-up). If this pin is high then the decoder
outputs (Q1 to Q4) are enabled. If it is low then the outputs go into their high-impedance state.
There is an internal pull-up at this pin.
Q1 to Q4 (Three-State Outputs). When the TOE pin is high these pins output the code in the
output latch which corresponds to the last valid tone-pair detected. They go into their high
impedance state when the TOE pin is low.
Low Frequency Output. Square wave output from the low group zero crossing detector
Filter Low Tones. Sine wave output from the low group filter circuit.
Delayed Steering (Digital Output). This pin follows the ESt and SVGT pins. It goes high to
indicate that a new tone-pair has been detected and the corresponding code has been loaded
into the output latch. It goes low to indicate that a new tone-pair is expected.
Early Steerlng (Digital Output). This pin goes high when the digital detection algorithm
decides that there is a valid DTMF input. It goes low as soon as the algorithm decides that there
is no valid DTMF input.
In normal use this pin is used to drive an external guard time circuit which in turn drives the
SUGT pin.
Steerlng / Guard Time (Voltage Input / Digltal Output). This pin follows the ESt pin. When
ESt pin changes state this pin acts as an input and monitors the voltage developed here by the
ESt pin acting through the external guard time circuit.
When the voltage reaches the internally generated VTSI level then this pin acts as an output
and pulls itself fully to the state of the ESt pin. When this pin goes fully high a new code is
loaded into the output latch and the StD pin goes high. When this pin goes fully low the device
prepares itself for a new tone-pair and the StD pin goes low.
Positive Supply (Power Input). This is the positive power supply for the device. It is normally
5V.
Note: 1. Figures in brackets are for HP28 package.
6
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