MT48LC4M32B2TG Просмотр технического описания (PDF) - Micron Technology

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MT48LC4M32B2TG

1 Meg x 32 x 4 Banks SDR SDRAM

Micron Technology 

128Mb: x32 SDRAM

General Description

General Description

The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing

134,217,728 bits. It is internally configured as a quad-bank DRAM with asynchronous

interface (all signals are registered on the positive edge of the clock signal, CLK). Each of

the 33,554,432-bit banks is organized as 4096 rows by 256 columns by 32 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed se-

quence. Accesses begin with the registration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the

bank; A[11:0] select the row).The address bits registered coincident with the READ or

WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8

locations, or the full page, with a burst terminate option. An auto precharge function

may be enabled to provide a self-timed row precharge that is initiated at the end of the

burst sequence.

The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-

tion. This architecture is compatible with the 2n rule of prefetch architectures, but it al-

so allows the column address to be changed on every clock cycle to achieve a high-

speed, fully random access. Precharging one bank while accessing one of the other

three banks will hide the precharge cycles and provide seamless, high-speed, random-

access operation.

The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh

mode is provided, along with a power-saving, power-down mode. All inputs and out-

puts are LVTTL-compatible.

The devices offer substantial advances in DRAM operating performance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks to hide precharge time, and

the capability to randomly change column addresses on each clock cycle during a burst

access.

Automotive Temperature

The automotive temperature (AT) option adheres to the following specifications:

• 16ms refresh rate

• Self refresh not supported

• Ambient and case temperature cannot be less than –40°C or greater than 105°C

PDF: 09005aef80872800

128mb_x32_sdram.pdf - Rev. U 04/13 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2001 Micron Technology, Inc. All rights reserved.

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