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MT46V4M32

DOUBLE DATA RATE (DDR) SDRAM

Micron Technology 

SET command with bits A7 and A9-A11 each set to zero,

bit A8 set to one, and bits A0-A6 set to the desired

values. Although not required by the Micron device,

JEDEC specifications recommend when a LOAD MODE

REGISTER command is issued to reset the DLL, it

should always be followed by a LOAD MODE REGIS-

TER command to select normal operating mode.

All other combinations of values for A7-A11 are re-

served for future use and/or test modes. Test modes

and reserved states should not be used because un-

known operation or incompatibility with future ver-

sions may result.

EXTENDED MODE REGISTER

The extended mode register controls functions be-

yond those controlled by the mode register; these ad-

ditional functions are DLL enable/disable. These func-

tions are controlled via the bits shown in Figure 3. The

extended mode register is programmed via the LOAD

MODE REGISTER command to the mode register (with

BA0 = 1 and BA1 = 0) and will retain the stored informa-

tion until it is programmed again or the device loses

power. Although not required by the Micron device,

the enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode regis-

ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the

controller must wait the specified time before initiat-

ing any subsequent operation. Violating either of these

requirements could result in unspecified operation.

Although not required by Micron, JEDEC recommends

a LOAD MODE REGISTER command be issued to the

mode register (BA0/BA1 both LOW) to reset the DLL.

Output Drive Strength

The reduced drive strength for all outputs are specified

to be SSTL2, Class I. The x32 supports both reduced and

matched impedance drive strengths. This option is in-

tended for the support of the lighter load and/or point-to-

point environments. The selection of the reduced drive

strength will alter the DQs and DQSs from SSTL2, Class

I drive strength to a reduced drive strength, which is

approximately 54 percent of the SSTL2, Class II drive

strength.

ADVANCE

128Mb: x32

DDR SDRAM

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization

and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-

tion. (When the device exits self refresh mode, the DLL

is enabled automatically.) Any time the DLL is enabled,

200 clock cycles must occur before a READ command

can be issued. The DLL must be reset any time the

clock frequency is changed followed by 200 clock cycles.

Figure 3

Extended Mode Register Definition

BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

13 12 11 10 9 8 7 6 5 4 3 2 1 0 Extended Mode

11 01

RFU2

DS

RFU2

DS DLL Register (Ex)

E0

DLL

0

Enable

1

Disable

E6 E1 Drive Strength

0 0 Reserved

01

Half

1 0 Reserved

1 1 Matched

NOTE: 1. E13 and E12 (BA0 and BA1) must be 1, 0 to select the

Extended Mode Register (vs. the base Mode Register).

2. Reserved for future use. Set values to 0.

128Mb: x32 DDR SDRAM

4M32DDR_B.p65 – Rev. B, Pub. 7/02

10

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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