MSC23140D-60BS10 Просмотр технического описания (PDF) - Oki Electric Industry

Номер в каталоге

Компоненты Описание

производитель

MSC23140D-60BS10

1,048,576-word x 40-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE

Oki Electric Industry 

Semiconductor

MSC23140D

Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles

(/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved.

2. The AC characteristics assumes tT = 5ns.

3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT) are

measured between VIH and VIL.

4. This parameter is measured with a load circuit equivalent to 2TTL loads and 100pF.

5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met.

tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then

the access time is controlled by tCAC.

6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met.

tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then

the access time is controlled by tAA.

7. tOFF(Max.) and tOEZ(Max.) define the time at which the output achieves the open circuit condition and are

not referenced to output voltage levels.

8. tRCH or tRRH must be satisfied for a read cycle.

9. tWCS, tCWD, tRWD and tCPWD are not restrictive operating parameters. They are included in the data sheet

as electrical characteristics only. If tWCS ≥ tWCS(Min.), the cycle is an early write cycle and the data out will

remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD(Min.), tRWD ≥ tRWD(Min.),

tAWD ≥ tAWD(Min.) and tCPWD ≥ tCPWD(Min.), the cycle is a read modify write cycle and data out will contain

data read from the selected cell; if neither or the above sets of conditions is satisfied, the conditions of

the data out (at access time) is indeterminate.

10. These parameters are referenced to /CAS leading edge in an early write cycle, and to /WE leading edge

in an /OE control write cycle or a read modify write cycle.

11. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is

latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet

is a 2-bit parallel test function. CA0 is not used. In a read cycle, if all internal bits are equal, the DQ pin

will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level.

The test mode is cleared and the memory device returned to its normal operating state by a /RAS only

refresh or /CAS before /RAS refresh cycle.

12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.

These parameters should be specified in test mode cycle by adding the above value to the specified

value in this data sheet.

Share Link: