MRF24J40-I/MM Просмотр технического описания (PDF) - Microchip Technology
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MRF24J40-I/MM Datasheet PDF : 66 Pages
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MRF24J40
REGISTER 2-2: RFCTRL7: RF CONTROL REGISTER 7
R/W-0
R/W-0
U-0
U-0
U-0
SLPCLK<7:6>
—
—
—
bit 7
U-0
R/W-0
R/W-0
—
CLKDIV<1:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-2
bit 1-0
SLPCLK7:SLPCLK6: Sleep Clock Selection bits
00 = None
01 = External crystal
10 = Internal ring oscillator
11 = Reserved
Unimplemented: Read as ‘0’
CLKDIV1:CLKDIV0: MRF24J40 Clock Output Frequency bits
00 = 2.5 MHz
01 = 5 MHz
10 = 10 MHz
11 = 20 MHz
To create a clean clock signal, the CLKOUT pin is held
low for a period when power is first applied. After the
Power-on Reset ends, the Oscillator Start-up Timer
(OST) will begin counting. When the OST expires, the
CLKOUT pin will begin outputting its default frequency
of 2.5 MHz (main clock divided by 8).
2.4 RF Output
RFP and RFN are the differential RF input/output pins.
These pins are connected to the antenna of the system,
as seen in the example circuit diagram in Figure A-1. L5
is an RF choke. This inductor filters out non 2.4 GHz
voltages. L3, L4, C37 and C43 act as a balun. The balun
converts a differential unbalanced input and converts it
to a balanced singled-ended output and visa versa. L1,
C23 and C38 form a pi-type matching circuit to match
the impedance of the balun to the impedance of the
antenna. This circuit is not required if the impedance of
the balun matches the antenna impedance. Refer
to Appendix A.1 “Layout Considerations and RF
Measurements” for more details about board layout
and part selection concerning the RF output pins.
DS39776A-page 8
Advance Information
© 2006 Microchip Technology Inc.
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