MK2058-01 Просмотр технического описания (PDF) - Integrated Circuit Systems
Номер в каталоге
Компоненты Описание
производитель
MK2058-01 Datasheet PDF : 10 Pages
| |||
MK2058-01
Communications Clock Jitter Attenuator
2. Adjust the voltage on pin 5 to 3.3V. Measure and
record the frequency of the same output.
To calculate the centering error:
Error = 106x (---f--3--.--0---V----–-----f--t--a--r--g---ef--t-t-a-)--r-+g---e--(-t--f--0---V----–-----f-t--a---r--g---e---t--) – errorxtal
Where:
ftarget = nominal crystal frequency
errorxtal =actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±15 ppm, adjustment
is not needed for most applications. If the centering
error is more than 15 ppm negative, the PCB has too
much stray capacitance and will need to be redone with
a new layout to reduce stray capacitance. Alternately,
the crystal may be re-specified for a higher lower load
capacitance. Contact ICS MicroClock for details. If the
centering error is more than 15 ppm positive, add
identical fixed centering capacitors from each crystal
pin to ground. The value for each of these caps (in pF)
is given by:
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied
by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (less than ±15ppm).
Recommended PCB Layout
G
For m inimum output clock jitter,
device VDD connections should
be made to comm on bulk
decoupling device (see text).
For m inimum output clock jitter,
rem ove ground and power plane
within this entire area. Also route
all other traces away from this area.
G
G
G
G
1
20
2
G 19
3
18
4
17
5
16
6G
15
7
G
14
8G
13
NC
9
12
10
11
G
Legend:
G = Ground
C o n n e c tio n
MDS 2058-01 B
7
Revision 071001
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
Share Link: 