MK2058-01 Просмотр технического описания (PDF) - Integrated Circuit Systems
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MK2058-01 Datasheet PDF : 10 Pages
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MK2058-01
Communications Clock Jitter Attenuator
Recommended Power Supply Connection
for Optimal Device Performance
Connection to 3.3V
Pow er Plane
Ferrite
Bead
VD D Pin
VD D Pin
Bulk Decoupling Capacitor
(such as 1 µF Tantalum)
VD D Pin
0.01 µF D ecoupling C apacitors
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground, shown as CL in the External Component
Schematic. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no via’s)
been the crystal and device.
In most cases the load capacitors will not be required.
They should not be stuffed on the prototype evaluation
board as the indiscriminate use of these trim capacitors
will typically cause more crystal centering error than
their absence. If the need for the load capacitors is later
determined, the values will fall within the 1-4 pf range.
The need for, and value of, these trim capacitors can
only be determined at prototype evaluation. Please
refer to the Optimization of Crystal Load Capacitors
section for more information.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed. Please also refer to the Recommended PCB
Layout drawing on Page 7.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The loop filter components must also be placed
close to the CHGP and VIN pins. C2 should be closest
to the device. Coupling of noise from other system
signal traces should be minimized by keeping traces
short and away from active signal traces. Use of vias
should be avoided.
3) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
4) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock output.
5) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the MK2058-01.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
The ICS Applications Note MAN05 may also be
referenced for additional suggestions on layout of the
crystal section.
Optimization of Crystal Load
Capacitors
The concept behind the optional crystal load capacitors
was introduced previously in this data sheet (see
Crystal Load Capacitor section on Page 5). To
determine the need for and value of these capacitors,
you will need a PCB of your final layout, a frequency
counter capable of less than 10 ppm resolution and
accuracy, two power supplies, and some samples of
the crystals which you plan to use in production, along
with measured initial accuracy for each crystal at the
specified crystal load capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD to 3.3V. Connect pin 5 to the second
power supply. Adjust the voltage on pin 5 to 0V.
Measure and record the frequency of the CLK output.
MDS 2058-01 B
6
Revision 071001
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q www.icst.com
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