MAX9092 Просмотр технического описания (PDF) - Maxim Integrated
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MAX9092 Datasheet PDF : 11 Pages
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MAX9092/MAX9093/MAX9094/MAX9095
General-Purpose, Low-Voltage,
Dual/Quad, Tiny Pack Comparators
Choose R1 and R2 to be large enough as not to exceed
the amount of current the reference can supply.
The source current required is VREF/(R1 + R2).
The sink current is (VOUT(HIGH) - VREF) x (R1 + R2).
Choose RL to be large enough to avoid drawing excess
current, yet small enough to supply the necessary cur-
rent to drive the load. RL should be between 1kI and
10kI. Choose R1 to be much larger than RL to avoid
lowering VOUT(HIGH) ir raising VOUT(LOW).
Board Layout and Bypassing
Use 0.1FF bypass capacitors from VDD to VSS. To maxi-
mize performance, minimize stray inductance by putting
this capacitor close to the VDD pin and reducing trace
lengths. For slow-moving input signals (rise time > 1ms),
use a 1nF capacitor between IN+ and IN- to reduce high
frequency noise.
PROCESS: BiCMOS
Chip Information
Ordering Information
PART
MAX9092AKA+
MAX9092AUA+*
MAX9093AKA+
MAX9093AUA+*
MAX9094ASD+*
MAX9094AUD+*
MAX9095ASD+*
MAX9095AUD+*
TEMP RANGE
PIN-
PACKAGE
-40°C to +125°C 8 SOT23
-40°C to +125°C 8 FMAX
-40°C to +125°C 8 SOT23
-40°C to +125°C 8 FMAX
-40°C to +125°C 14 SO
-40°C to +125°C 14 TSSOP
-40°C to +125°C 14 SO
-40°C to +125°C 14 TSSOP
TOP
MARK
+AESO
—
+AESP
—
—
—
—
—
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product—Contact factory for availability.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
8 SOT23
8 µMAX
14 SO
14 TSSOP
PACKAGE
CODE
K8+5
U8+1
S14+1
U14+1
OUTLINE
NO.
21-0078
21-0036
21-0041
21-0066
LAND
PATTERN NO.
90-0176
90-0092
90-0112
90-0113
10
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