MAX9205 Просмотр технического описания (PDF) - Maxim Integrated
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MAX9205 Datasheet PDF : 13 Pages
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MAX9205/MAX9207
10-Bit Bus LVDS Serializers
ABSOLUTE MAXIMUM RATINGS
AVCC, DVCC to GND..........................……………-0.3V to +4.0V
IN_, SYNC1, SYNC2, EN, TCLK_R/F, TCLK,
PWRDN to GND......................................-0.3V to (VCC + 0.3V)
OUT+, OUT- to GND .............................................-0.3V to +4.0V
Output Short-Circuit Duration.....................................Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
ESD Protection (Human Body Model, OUT+, OUT-) ...........±8kV
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
SSOP
Junction-to-Ambient Thermal Resistance (θJA)...............68°C/W
Junction-to-Case Thermal Resistance (θJC)......................25°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC ELECTRICAL CHARACTERISTICS
(VAVCC = VDVCC = +3.0V to +3.6V, RL = 27Ω ±1% or 50Ω ±1%, CL = 10pF, TA = -40°C to +85°C. Typical values are at VAVCC =
VDVCC = +3.3V and TA = +25°C, unless otherwise noted.) (Notes 2, 3, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, SYNC1, SYNC2, TCLK, TCLK_R/F, PWRDN)
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
Input Current
IIN
BUS LVDS OUTPUTS (OUT+, OUT-)
Differential Output Voltage
VOD
VIN_ = 0V or V_VCC
Figure 1
RL = 27Ω
RL = 50Ω
2.0
GND
-20
200
250
Change in VOD Between
Complementary Output States
∆VOD Figure 1
Output Offset Voltage
VOS
Figure 1
0.9
Change in VOS Between
Complementary Output States
∆VOS Figure 1
Output Short-Circuit Current
IOS
VOUT+ or VOUT- = 0V,
IN0 to IN9 = PWRDN = EN = high
Output High-Impedance Current
IOZ
VPWRDN or VEN = 0.8V,
VOUT+ or VOUT- = 0V or V_VCC
-10
Power-Off Output Current
IOX
V_VCC = 0V, VOUT+ or VOUT- = 0V or 3.6V
-10
POWER SUPPLY
Supply Current
16MHz
RL = 27_ or 50_
MAX9205
40MHz
ICC
worst-case pattern
(Figures 2, 4)
40MHz
MAX9207
66MHz
Power-Down Supply Current
ICCX
PWRDN = low
TYP
286
460
1
1.15
3
-13
23
34
32
45
MAX UNITS
VCC
V
0.8
V
+20
µA
400
mV
600
mV
35
mV
1.3
V
35
mV
-15
mA
+10
µA
+10
µA
35
45
mA
50
60
8
mA
2
Maxim Integrated
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