MAX9208EAI(2001) Просмотр технического описания (PDF) - Maxim Integrated

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MAX9208EAI
(Rev.:2001)

10-Bit Bus LVDS Deserializers

Maxim Integrated 

10-Bit Bus LVDS Deserializers

Test Circuits/Timing Diagrams (continued)

VCC

RIN2

LVCMOS/LVTTL

OUTPUT

VCC - 0.3V

RI+

RIN1

TO DESERIALIZING

CIRCUITRY

CL

15pF

80%

80%

RIN1

RI-

20%

tCLH

20%

tCHL

Figure 2. Input Fail-Safe Circuit

Figure 3. LVCMOS/LVTTL Output Load and Transition Times

START

START

START

BIT

SYMBOL N

END BIT

SYMBOL N+1

END BIT

RI

0 1 2 3 4 5 6 7 8 9 BIT 0 1 2 3 4 5 6 7 8 9 BIT 0 1 2

tDD

RCLK

RCLK_R/F = HIGH

ROUT_

SYMBOL N-1

SYMBOL N

Figure 4. Input-to-Output Delay

+7V FOR tLZR AND tZLR

OPEN FOR tHZR AND tZHR

RCLK

RCLK_R/F = LOW

RCLK

RCLK_R/F = HIGH

ROUT_

50%

tROS

DATA VALID

BEFORE RCLK

50%

tROH

DATA VALID

AFTER RCLK

Figure 5. Data Valid Times

500Ω

450Ω

CL

SCOPE

50Ω

REN

tLZR

ROUT_ VOL

RCLK VOH

tHZR

1.5V

tZLR

tZHR

VOL +0.5V

VOH -0.5V

Figure 6. High-Impedance Test Circuit and Timing

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