MAX9208EAI(2001) Просмотр технического описания (PDF) - Maxim Integrated

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MAX9208EAI
(Rev.:2001)

10-Bit Bus LVDS Deserializers

Maxim Integrated 

10-Bit Bus LVDS Deserializers

AC ELECTRICAL CHARACTERISTICS (continued)

(AVCC = DVCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.15V to 1.2V, common-mode voltage VCM = |VID/2| to

2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVCC = DVCC = +3.3V, VCM = +1.1V, |VID| = 0.2V,

TA = +25°C.) (Notes 4, 5)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

PLL Lock Time (from Start of

Sync Patterns)

tDSR2

PLL locked to stable REFCLK; supply

stable; static input; measured from start

of sync patterns at input to LOCK

transition low; Figure 8

42 x tRFCP ns

LOCK High-Z to High-State

Delay

tZHLK Figure 7

30

ns

16MHz

1300

MAX9206

40MHz

720

Input Jitter Tolerance

tJT

Figure 9

40MHz

720

ps

MAX9208

60MHz

320

Note 1: Short one output at a time. Do not exceed the Absolute Maximum continuous power dissipation.

Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Voltages are referenced to ground

except VTH, VTL, and VID, which are differential input voltages.

Note 3: DC parameters are production tested at TA = +25°C and guaranteed by design and characterization over operating temper-

ature range.

Note 4: AC parameters guaranteed by design and characterization.

Note 5: CL includes scope probe and test jig capacitance.

Note 6: tRCP is determined by the period of TCLK, which is the reference clock of the serializer driving the deserializer. The frequen-

cy of TCLK must be within ±400ppm of the REFCLK frequency.

4 _______________________________________________________________________________________

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