MAX9208EAI(2001) Просмотр технического описания (PDF) - Maxim Integrated
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MAX9208EAI Datasheet PDF : 12 Pages
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10-Bit Bus LVDS Deserializers
AC ELECTRICAL CHARACTERISTICS
(AVCC = DVCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.15V to 1.2V, common-mode voltage VCM = |VID/2| to
2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVCC = DVCC = +3.3V, VCM = +1.1V, |VID| = 0.2V,
TA = +25°C.) (Notes 4, 5)
PARAMETER
SYMBOL
CONDITIONS
REFERENCE CLOCK TIMING REQUIREMENTS (REFCLK)
REFCLK Frequency
MAX9206
fRFF
MAX9208
REFCLK Frequency Variation
RFFV
REFCLK Period
tRFCP
MAX9206
MAX9208
REFCLK Duty Cycle
RFDC
REFCLK Input Transition Time
tRFTT
SWITCHING CHARACTERISTICS
Recovered Clock (RCLK) Period
(Note 6)
tRCP
MAX9206
MAX9208
Low-to-High Transition Time
tCLH
Figure 3
High-to-Low Transition Time
tCHL Figure 3
Deserializer Delay
tDD
Figure 4
MAX9206, 40MHz
MAX9208, 60MHz
MIN
TYP
MAX UNITS
16
40
-200
25
16.666
30
40
MHz
60
200
ppm
62.5
ns
25
50
70
%
3
6
ns
25
16.666
62.5
ns
25
1.5
3
ns
2
3
ns
1.75 x tRCP 1.75 x tRCP 1.75 x tRCP
+2
+ 3.3
+ 6.5
ns
1.75 x tRCP 1.75 x tRCP 1.75 x tRCP
+ 1.1
+ 3.3
+ 5.6
ROUT_ Data Valid Before RCLK
ROUT_ Data Valid After RCLK
RCLK Duty Cycle
OUTPUT High-to-High
Impedance Delay
tROS
tROH
tRDC
tHZR
Figure 5
Figure 5
CL = 5pF, Figure 6
0.4 x tRCP 0.5 x tRCP
ns
0.4 x tRCP 0.5 x tRCP
ns
43
50
57
%
8
ns
OUTPUT Low-to-High
Impedance Delay
tLZR
CL = 5pF, Figure 6
8
ns
OUTPUT High-Impedance to
High-State Delay
tZHR CL = 5pF, Figure 6
6
ns
OUTPUT High-Impedance to
Low-State Delay
tZLR
CL = 5pF, Figure 6
6
ns
PLL Lock Time (from PWRDN
Transition High)
tDSR1
Sync patterns at input; supply and
REFCLK stable; measured from
PWRDN transition high to LOCK
transition low; Figure 7
(2048 + 42) ns
x tRFCP
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