MAX9208(2001) Просмотр технического описания (PDF) - Maxim Integrated
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MAX9208 Datasheet PDF : 12 Pages
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10-Bit Bus LVDS Deserializers
Table 2. Input/Output Function Table
LOGIC INPUTS
REN
PWRDN
CONDITIONS
X
Low
Power applied and stable
Low
High
Deserializer initialized
High
X = don’t care
High
Deserializer initialized
OUTPUTS
Power-down mode. PLL is stopped. Current consumption is reduced
to 400µA (typ). ROUT_, RCLK, and LOCK are high impedance.
RCLK and ROUT_ are high impedance. LOCK is active, indicating
the serial input status.
RCLK and ROUT_ are active. LOCK is active, indicating the serial
input status.
Topologies
The MAX9206/MAX9208 deserializers can operate in a
variety of topologies. Examples of double-terminated
point-to-point and point-to-point broadcast are shown
in Figures 10 and 11. Use 1% surface-mount termina-
tion resistors.
A point-to-point interface terminated at each end in the
characteristic impedance of the cable or PC board
traces is shown in Figure 10. The total load seen by the
serializer is 50Ω. The double termination typically
reduces reflections compared to a single 100Ω termi-
nation. A single 100Ω termination at the deserializer
input is feasible and makes the differential signal swing
larger.
A point-to-point version of a multidrop bus is shown in
Figure 11. The low-jitter MAX9150 10-port repeater is
used to reproduce and transmit the serializer output
over 10 double-terminated point-to-point links.
Compared to a bus, more interconnect is traded for
robust hot-plug capability.
The repeater eliminates nine serializers compared to 10
individual point-to-point serializer-to-deserializer con-
nections. Since repeater jitter is a component of the
total jitter seen at the deserializer input (along with
other sources of jitter), a low-jitter repeater is essential
in most high data-rate applications.
Board Layout
A four-layer PC board providing separate power,
ground, and signal layers is recommended. Keep the
LVTTL/LVCMOS inputs and outputs separated from the
BLVDS inputs to prevent coupling into the BLVDS lines.
Pin Configuration
TOP VIEW
AGND 1
RCLK_R/F 2
REFCLK 3
AVCC 4
RI+ 5
RI- 6
PWRDN 7
REN 8
RCLK 9
LOCK 10
AVCC 11
AGND 12
AGND 13
DGND 14
MAX9206/
MAX9208
SSOP
28 ROUT0
27 ROUT1
26 ROUT2
25 ROUT3
24 ROUT4
23 DVCC
22 DGND
21 DVCC
20 DGND
19 ROUT5
18 ROUT6
17 ROUT7
16 ROUT8
15 ROUT9
Chip Information
TRANSISTOR COUNT: 9602
PROCESS: CMOS
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