MAX8833 Просмотр технического описания (PDF) - Maxim Integrated

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MAX8833

Dual, 3A, 2MHz Step-Down Regulator

Maxim Integrated 

Dual, 3A, 2MHz Step-Down Regulator

Pin Description (continued)

PIN

27, 28

29

30

31

32

—

NAME

IN1

EN1

COMP1

FB1

SS1

EP

FUNCTION

Power-Supply Input for Regulator 1. The voltage range is 2.35V to 3.6V. Connect two 10µF and one 0.1µF

ceramic capacitors from IN1 to PGND1.

Enable Input for Regulator 1. Drive EN1 high to enable regulator 1, or low for shutdown. For always-on

operation, connect EN1 to VDD.

Compensation for Regulator 1. COMP1 is the output of the internal voltage-error amplifier. Connect external

compensation network from COMP1 to FB1. See the Compensation Design section. COMP1 is internally

pulled to GND when the output is shut down.

Feedback Input for Regulator 1. Connect FB1 to the center of an external resistor-divider from the output to

GND to set the output voltage from 0.6V to 90% of VIN1. FB1 is high impedance when the IC is shut down.

Soft-Start for Regulator 1. Connect a capacitor from SS1 to GND to set the startup time. See the Setting the

Soft-Start Time section. When E1 is disabled (pulled low), or Regulator 1 is in shutdown mode due to a fault

condition, SS1 is internally pulled low with 335Ω resistor.

Exposed Pad. Connect the exposed pad to the power ground plane.

Detailed Description

PWM Controller

The controller logic block is the central processor that

determines the duty cycle of the high-side MOSFET

under different line, load, and temperature conditions.

Under normal operation, where the current-limit and

temperature protection are not triggered, the control

logic block takes the output from the PWM comparator

and generates the driver signals for both high-side and

low-side MOSFETs. It also contains the break-before-

make logic and the timing for charging the bootstrap

capacitors. The error signal from the voltage-error ampli-

fier is compared with the ramp signal generated by the

oscillator at the PWM comparator and, thus, the required

PWM signal is produced. The high-side switch is turned

on at the beginning of the oscillator cycle and turns off

when the ramp voltage exceeds the VCOMP signal or the

current-limit threshold is exceeded. The low-side switch

is then turned on for the remainder of the oscillator

cycle. The two switching regulators operate at the same

switching frequency with 180° phase shift to reduce the

input-capacitor ripple current requirement. Figure 1

shows the MAX8833 functional diagram.

Current Limit

The MAX8833 provides both peak and valley current limits

to achieve robust short-circuit protection. During the

high-side MOSFET’s on-time, if the drain-source current

reaches the peak current-limit threshold (specified in

the Electrical Characteristics table), the high-side MOS-

FET turns off and the low-side MOSFET turns on, allow-

ing the current to ramp down. At the next clock, the

high-side MOSFET is turned on only if the inductor cur-

rent is below the valley current limit. Otherwise, the PWM

cycle is skipped to continue ramping down the inductor

current. When the inductor current stays above the valley

current limit for 12µs and the FB_ is below 0.7 x VREFIN,

the regulator enters hiccup mode. During hiccup mode,

the SS_ capacitor is discharged to zero and the soft-start

sequence begins after a predetermined time period.

Undervoltage Lockout (UVLO)

When the VDD supply voltage drops below the falling

undervoltage threshold (typically 1.9V), the MAX8833

enters its undervoltage lockout mode (UVLO). UVLO

forces the device to a dormant state until the input volt-

age is high enough to allow the device to function reli-

ably. In UVLO, LX_ nodes of both regulators are in the

high-impedance state. PWRGD1 and PWRGD2 are

forced low in UVLO. When VVDD rises above the rising

undervoltage threshold (typically 2V), the IC powers up

normally as described in the Startup and Sequencing

section.

The UVLO circuitry also monitors the IN1 and IN2 sup-

plies. When the IN_ voltage drops below the falling

undervoltage threshold (typically 1.9V), the correspond-

ing regulator shuts down, and corresponding PWRGD_

goes low. The regulator powers up when VIN_ rises

above the rising undervoltage threshold (typically 2V).

Power-Good Output (PWRGD_)

PWRGD1 and PWRGD2 are open-drain outputs that

indicate when the corresponding output is in regulation.

PWRGD1 is high impedance when VREFIN ≥ 0.54V and

VFB1 ≥ 0.9 x VREFIN. PWRGD1 is low when VREFIN <

0.54V, EN1 is low, VVDD or VIN1 is below VUVLO, the

thermal-overload protection is activated, or when VFB1

< 0.9 x VREFIN.

8 _______________________________________________________________________________________

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