M69AR024BL80ZB8T Просмотр технического описания (PDF) - STMicroelectronics

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M69AR024BL80ZB8T

16 Mbit (1M x16) 1.8V Supply, Asynchronous PSRAM

STMicroelectronics 

M69AR024B

OPERATION

Operational modes are determined by device con-

trol inputs W, E1, E2, LB and UB as summarized

in the Operating Modes table (see Table

2., Operating Modes).

Power Up Sequence

Because the internal control logic of the

M69AR024B needs to be initialized, the following

power-on procedure must be followed before the

memory is used:

– Apply power and wait for VCC to stabilize

– Wait 300µs while driving both Chip Enable

signals (E1 and E2) High

Read Mode

The device is in Read mode when:

– Write Enable (W) is High and

– Output Enable (G) Low and

– Upper Byte Enable (UB) or Lower Byte

Enable (LB) is Low, or both

– the two Chip Enable signals are asserted

(E1 is Low, and E2 is High).

The time taken to enter Read mode (tELQV, tGLQV

or tBLQV) depends on which of the above signals

was the last to reach the appropriate level.

Data out (DQ15-DQ0) may be indeterminate

during tELQX, tGLQX and tBLQX, but data will always

be valid during tAVQV.

Write Mode

The device is in Write mode when

– Write Enable (W) is Low and

– Upper Byte Enable (UB) or Lower Byte

Enable (LB) is Low, or both

– the two Chip Enable signals are asserted

(E1 is Low, and E2 is High).

The Write cycle begins just after the event (the fall-

ing edge) that causes the last of these conditions

to become true (tAVWL or tAVEL or tAVBL).

The Write cycle is terminated by the earlier of a ris-

ing edge on Write Enable (W) or Chip Enable (E1).

If the device is in Write mode (Chip Enable (E1) is

Low, Output Enable (G) is Low, Upper Byte En-

able (UB) or Lower Byte Enable (LB) is Low), then

Write Enable (W) will return the outputs to high im-

pedance within tWLQZ of its falling edge. Care must

be taken to avoid bus contention in this type of op-

eration. Data input must be valid for tDVWH before

the rising edge of Write Enable (W), for tDVEH be-

fore the rising edge of Chip Enable (E1), or for tD-

VBH before the rising edge of Byte Enable (LB,UB),

whichever occurs first, and remain valid for tWHDZ,

tEHDZ or tBHDZ.

Standby Mode

The device is in Standby mode when:

– Chip Enable (E1) is High and

– Chip Enable (E2) is High

The input/output buffers and the decoding/control

logic are switched off, but the dynamic array con-

tinues to be refreshed. In this mode, the memory

current consumption, ISB, is reduced, and the data

remains valid.

Deep Power-down Mode

The device is in Deep Power-down mode when:

– Chip Enable (E2) is Low

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