MAX709CPA Просмотр технического описания (PDF) - Maxim Integrated

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MAX709CPA

Power-Supply Monitor with Reset

Maxim Integrated 

Power-Supply Monitor with Reset

____________________Pin Description

PIN

1, 4, 5,

6, 8

2

NAME

N.C.

VCC

FUNCTION

No Connect. There is no internal

connection to this pin.

+5V, +3.3V, or +3V Supply Voltage

3

GND Ground

Reset Output remains low while VCC is

7

RESET

below the reset threshold, and for

280ms after VCC rises above the reset

threshold.

__________Applications Information

Negative-Going VCC Transients

In addition to issuing a reset to the microprocessor

(µP) during power-up, power-down, and brownout con-

ditions, the MAX709 is relatively immune to short dura-

tion negative-going VCC transients (glitches).

Figure 1 shows typical transient duration vs. reset com-

parator overdrive, for which the MAX709 does not gen-

erate a reset pulse. The graph was generated using a

negative-going pulse applied to VCC, starting 1.5V

above the actual reset threshold and ending below it

by the magnitude indicated (reset comparator over-

drive). The graph indicates the typical maximum pulse

width that a negative-going VCC transient may have

without causing a reset pulse to be issued. As the

magnitude of the transient increases (goes farther

below the reset threshold), the maximum allowable

pulse width decreases. Typically, for the

MAX709L/MAX709M, a VCC transient that goes 100mV

below the reset threshold and lasts 40µs or less will not

cause a reset pulse to be issued.

150

TA = +25°C

100

MAX709L/M

50

10ns

MAX709R/S/T

0

10

100

1k

10k

RESET COMPARATOR OVERDRIVE, VTH - VCC (mV)

Figure 1. Maximum Transient Duration without Causing a

Reset Pulse vs. Reset Comparator Overdrive

A 0.1µF bypass capacitor mounted as close as possible

to pin 2 (VCC) provides additional transient immunity.

Ensuring a Valid RESET Output

Down to VCC = 0V

When VCC falls below 1V, the MAX709 RESET output

no longer sinks current—it becomes an open circuit.

Therefore, high-impedance CMOS logic inputs con-

nected to the RESET output can drift to undermined

voltages. This presents no problem in most applica-

tions, since most µP and other circuitry is inoperative

with VCC below 1V. However, in applications where the

RESET output must be valid down to 0V, adding a pull-

down resistor to the RESET pin will cause any stray

leakage currents to flow to ground, holding RESET low

(see Figure 2). The resistance value of R1 is not criti-

cal. It should be about 100kΩ, which is large enough

not to load RESET and small enough to pull RESET to

ground.

4 _______________________________________________________________________________________

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