MAX5364 Просмотр технического описания (PDF) - Maxim Integrated
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MAX5364 Datasheet PDF : 12 Pages
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Low-Cost, Low-Power, 6-Bit DACs with 3-Wire
Serial Interface in SOT23
VDD
REF
CURRENT-STEERING
OUT
DAC
CS
DIN
SCLK
CONTROL LOGIC
63
DATA LATCH
6
SERIAL INPUT REGISTER
MAX5363
MAX5364
MAX5365
GND
Figure 1. Functional Diagram
VREF
SW1
SW2
SW63
OUT
Figure 2. Current-Steering DAC Topology
Table 1. Unipolar Code Output Voltage
DAC CODE
[D11–D6]
OUTPUT VOLTAGE
MAX5363
MAX5364
MAX5365
111 111
100 000
000 001
000 000
2V × (63/64)
1V
31mV
0
4V × (63/64)
2V
63mV
0
0.9 × VDD ×
(63/64)
0.9 × VDD / 2
0.9 × VDD / 64
0
combination of resistive loads >10kΩ and capacitive
loads <50pF.
Power-On Reset
The MAX5363/MAX5364/MAX5365 have a power-on
reset circuit to set the DAC’s output to 0 when VDD is
first applied or when VDD dips below 1.7V (typ). This
ensures that unwanted DAC output voltages will not
occur immediately following a system startup, such as
after a loss of power. The output glitch on startup is typ-
ically less than 50mV.
Shutdown Mode
The MAX5363/MAX5364/MAX5365 include three soft-
ware-controlled shutdown modes that reduce the supply
current to <1µA. All internal circuitry is disabled, and a
known impedance is placed from OUT to GND to
ensure 0V while in shutdown. Table 2 details the three
shutdown modes of operation.
Digital Section
3-Wire Serial Interface
The MAX5363/MAX5364/MAX5365s’ digital interface is
a standard 3-wire connection compatible with
SPI/QSPI/MICROWIRE interfaces. The chip-select input
(CS) frames the serial data loading at the data-input pin
(DIN). Immediately following CS’s high-to-low transition,
the data is shifted synchronously and latched into the
input register on the rising edge of the serial clock input
(SCLK). After 16 bits have been loaded into the serial
8 _______________________________________________________________________________________
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