MAX533 Просмотр технического описания (PDF) - Maxim Integrated

Номер в каталоге

Компоненты Описание

производитель

MAX533

2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers

Maxim Integrated 

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

_______________Detailed Description

Serial Interface

At power-on, the serial interface and all digital-to-

analog converters (DACs) are cleared and set to code

zero. The serial data output (DOUT) is set to transition

on SCLK's falling edge.

The MAX533 communicates with microprocessors

through a synchronous, full-duplex, 3-wire interface

(Figure 1). Data is sent MSB first and can be transmit-

ted in one 4-bit and one 8-bit (byte) packet or in one

12-bit word. If a 16-bit word is used, the first four bits

are ignored. A 4-wire interface adds a line for LDAC

and allows asynchronous updating. The serial clock

(SCLK) synchronizes the data transfer. Data is transmit-

ted and received simultaneously.

Figure 2 shows the detailed serial-interface timing.

Please note that the clock should be low if it is stopped

between updates. DOUT does not go into a high-

impedance state if the clock idles or CS is high.

Serial data is clocked into the data registers in MSB-first

format, with the address and configuration information

preceding the actual DAC data. Data is clocked in on

SCLK’s rising edge while CS is low. Data at DOUT is

clocked out 12 clock cycles later, either at SCLK’s falling

edge (default or mode 0) or rising edge (mode 1).

Chip select (CS) must be low to enable the DAC. If CS

is high, the interface is disabled and DOUT remains

unchanged. CS must go low at least 40ns before the

first rising edge of the clock pulse to properly clock in

the first bit. With CS low, data is clocked into the

MAX533’s internal shift register on the rising edge of

the external serial clock. Always clock in the full 12 bits

because each time CS goes high the bits currently in

the input shift register are interpreted as a command.

SCLK can be driven at rates up to 10MHz.

THIS IS THE FIRST BIT SHIFTED IN

... DOUT

MSB

A1 A0 C1 C0 D7 D6

LSB

D1 D0

DIN

CONTROL AND

ADDRESS BITS

8-BIT DAC DATA

Serial Input Data Format and Control Codes

The 12-bit serial input format shown in Figure 3 com-

prises two DAC address bits (A1, A0), two control bits

(C1, C0), and eight bits of data (D7...D0).

The 4-bit address/control code configures the DAC as

shown in Table 1.

Load Input Register, DAC Registers Unchanged

(Single Update Operation)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

Address 0 1

8-Bit Data

(LDAC = H)

When performing a single update operation, A1 and A0

select the respective input register. At the rising edge

of CS, the selected input register is loaded with the cur-

rent shift-register data. All DAC outputs remain

unchanged. This preloads individual data in the input

register without changing the DAC outputs.

Load Input and DAC Registers

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

Address 1 1

8-Bit Data

(LDAC = H)

This command directly loads the selected DAC register at

CS’s rising edge. A1 and A0 set the DAC address. Current

shift-register data is placed in the selected input and DAC

registers.

For example, to load all four DAC registers simultaneously

with individual settings (DAC A = 0.5V, DAC B = 1V,

DAC C = 1.5V, and DAC D = 2V), four commands are

required. First, perform three single input register

update operations for DACs A, B, and C (C1 = 0). The

final command loads input register D and updates all

four DAC registers from their respective input registers.

Software “LDAC ” Command

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

0 10 0 xxx xx xxx

(LDAC = 1)

All DAC registers are updated with the contents of their

respective input registers at CS’s rising edge. With the

exception of using CS to execute, this performs the

same function as the asynchronous LDAC.

Figure 3. Serial Input Format

_______________________________________________________________________________________ 9

Share Link: