MAX533 Просмотр технического описания (PDF) - Maxim Integrated

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MAX533

2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers

Maxim Integrated 

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

12-BIT SERIAL WORD

LDAC

A1

A0

C1

C0 D7 . . . . . . . . D0

FUNCTION

0

0

0

1

8-bit DAC data

1

Load input register A; all DAC outputs unchanged.

0

1

0

1

8-bit DAC data

1

Load input register B; all DAC outputs unchanged.

1

0

0

1

8-bit DAC data

1

Load input register C; all DAC outputs unchanged.

1

1

0

1

8-bit DAC data

1

Load input register D; all DAC outputs unchanged.

0

0

1

1

8-bit DAC data

1

Load input register A; all DAC outputs updated

0

1

1

1

8-bit DAC data

1

Load input register B; all DAC outputs updated

1

0

1

1

8-bit DAC data

1

Load input register C; all DAC outputs updated

1

1

1

1

8-bit DAC data

1

Load input register D; all DAC outputs updated.

Software LDAC commands. Update all DACs from

0

1

0

0

XXXXXXXX

1

their respective input registers. Also bring the part out

of shutdown mode.

1

0

0

0

8-bit DAC data

X

Load all DACs with shift-register data. Also bring the

part out of shutdown mode.

1

1

0

0

XXXXXXXX

X

Software shutdown (provided PDE is high)

0

0

1

0

XXXXXXXX

X

UPO goes low.

0

1

1

0

XXXXXXXX

X

UPO goes high.

0

0

0

0

XXXXXXXX

X

No operation (NOP); shift data in shift registers.

Set DOUT phase—SCLK rising (mode 1). DOUT

1

1

1

0

XXXXXXXX

X

clocked out on rising edge of SCLK. All DACs updated

from their respective input registers.

Set DOUT phase—SCLK falling (mode 0). DOUT

1

0

1

0

XXXXXXXX

X

clocked out on falling edge of SCLK. All DACs up-

dated from their respective registers (default).

Load All DACs with Shift-Register Data

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

1 00 0

8-Bit Data

(LDAC = X)

All four DAC registers are updated with shift-register

data. This command allows all DACs to be set to any

analog value within the reference range. This command

can be used to substitute CLR if code 00 hex is pro-

grammed, which clears all DACs.

Software Shutdown

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 0 xxx xx xxx

(LDAC = X, PDE = H)

Shuts down all output buffer amplifiers, reducing sup-

ply current to 10µA max.

User-Programmable Output (UPO)

A1

A0

C1

C0

D7

D6

D5

D4

D3

D2

D1

D0

UPO

Output

0 0 1 0 x x x x x x x x Low

0 1 1 0 x x x x x x x x High

(LDAC = X)

User-programmable logic output for controlling another

device across an isolated interface. Example devices

are gain control of an amplifier, a 4mA to 20mA amplifi-

er, and a polarity output for a motor speed control.

No Operation (NOP)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 xxx xx xxx

(LDAC = X)

The NOP command (no operation) allows data to be

shifted through the MAX533 shift register without affect-

ing the input or DAC registers. This is useful in daisy

chaining (also see the Daisy Chaining Devices section).

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