MAX3881 Просмотр технического описания (PDF) - Maxim Integrated
Номер в каталоге
Компоненты Описание
производитель
MAX3881 Datasheet PDF : 11 Pages
| |||
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Pin Description
PIN
1, 15, 16, 17,
25, 33, 41,
49, 57, 62,
64
2
3
4, 7, 10, 13,
20, 22, 24,
26, 28, 30,
32, 34, 36,
38, 40, 42,
44, 46, 48,
50, 52, 54,
56, 58, 60
5
NAME
GND
FIL+
FIL-
VCC
PHADJ+
6
PHADJ-
8
SDI+
9
SDI-
11
SLBI+
12
SLBI-
14
SIS
18
19
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
PCLK+
PCLK-
PD0 to PD15
63
LOL
EP
Exposed Pad
FUNCTION
Ground
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
+3.3V Supply Voltage
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
Positive Serial Data Input. 2.488Gbps data stream.
Negative Serial Data Input. 2.488Gbps data stream.
Positive System Loopback Input. 2.488Gbps data stream.
Negative System Loopback Input. 2.488Gbps data stream.
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
Positive Parallel Clock PECL Output
Negative Parallel Clock PECL Output
Parallel Data Single-Ended PECL Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 2).
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩ pullup resistor).
The LOL monitor is valid only when a data stream is present on the inputs to the MAX3881.
Ground. This must be soldered to a circuit board for proper electrical and thermal performance
(see Package Information).
_______________________________________________________________________________________ 5
Share Link: 