MAX3881 Просмотр технического описания (PDF) - Maxim Integrated

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MAX3881

+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery

Maxim Integrated 

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

AC ELECTRICAL CHARACTERISTICS

(VCC = +3.0V to +3.6V, PECL loads = 50Ω to (VCC - 2V), TA = -40°C to +85°C, unless otherwise noted. Typical values are at

VCC = +3.3V, TA = +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Serial Data Rate

SDI

2.488

Gbps

Parallel Output Data Rate

155.52

Mbps

Parallel Clock-to-Data Output

Delay

tCLK-Q Figure 2

200

450

900

ps

f = 70kHz (Note 2)

2.31

3.3

Jitter Tolerance

f = 100kHz

f = 1MHz

1.74 2.41

0.38 0.57

UIp-p

f = 10MHz

0.28 0.46

Tolerated Consecutive Identical

Digits

>2,000

Bits

Input Return Loss (SDI±, SLBI±)

Output Edge Speed

tR, tF

100kHz to 2.5GHz

2.5GHz to 4.0GHz

20% to 80%

-18

dB

-11

800

ps

Note 1: AC characteristics are guaranteed by design and characterization.

Note 2: At jitter frequencies <70kHz, the jitter tolerance of the MAX3881 outperforms the ITU/Bellcore specifications.

SDI+

SDI-

(SDI+) - (SDI-)

Figure 1. Input Amplitude

25mV MIN

400mV MAX

VID

50mVp-p MIN

800mVp-p MAX

PCLK

PD0–PD15

tCLK-Q

Figure 2. Timing Parameters

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