MAX3815A Просмотр технического описания (PDF) - Maxim Integrated
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MAX3815A Datasheet PDF : 11 Pages
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TMDS Digital Video Equalizer for
HDMI/DVI Cables
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range, VCC.................................-0.5V to +4.0V
Voltage Range at Output CML Pins.....................-0.5V to +4.0V
Voltage Range at Input CML Pins, RES, VCC_T,
and GND_T............................................. -0.5V to (VCC + 0.7V)
Voltage Between Input CML Complementary Pair............ ±3.3V
Voltage Between Output CML Complementary Pair......... ±1.4V
Continuous Power Dissipation (TA = +70°C)
48-Pin TQFP (derate 36.2mW/°C above +70°C).........2896mW
Operating Junction Temperature Range.......... -55°C to +150°C
Storage Temperature Range............................ -55°C to +150°C
Die Attach Temperature...................................................+400°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.5V, TA = 0°C to +70°C. Typical values are at VCC = +3.3V, external terminations = 50Ω ±1%, MAX3815A in
automatic equalization mode (EQCONTROL = GND), TMDS rate = 250Mbps to 2.25Gbps, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Power-Supply Current
Clock present (CLKLOS = HIGH)
ICC
Clock and data absent (CLKLOS = LOW)
210 270
mA
12
Supply-Noise Tolerance
DC to 500kHz
200
mVP-P
EQUALIZER PERFORMANCE
Residual Output Jitter (Cables
Only) 0.25Gbps to 1.65Gbps
(Notes 1, 2, and 3)
1dB skin-effect loss at 825MHz
24dB skin-effect loss at 825MHz
0.05
UI
0.13 0.21
Residual Output Jitter (Cables
Only) 1.65Gbps to 2.25Gbps
(Notes 1, 2, and 3)
CID Tolerance
CONTROL AND STATUS
CLKLOS Assert Level
CML INPUTS (CABLE SIDE)
Differential Input-Voltage Swing
Common-Mode Input Voltage
Input Resistance
CML OUTPUTS (ASIC SIDE)
Differential Output-Voltage Swing
Output-Voltage High
Output-Voltage Low
Output Voltage During Clock
Absence (CLKLOS = LOW)
VID
VCM
RIN
VOD
1dB skin-effect loss at 825MHz
24dB skin-effect loss at 825MHz
0.1
UI
0.14 0.28
20
Bits
Differential peak-to-peak at EQ input
with max 225MHz clock (see the Typical
Operating Characteristics for more
information)
50
mVP-P
At cable input
Single-ended
800
VCC -
0.4
45
1000
50
1200
VCC +
0.1
55
mVP-P
V
W
50W load, each side OUTLEVEL = HIGH
to VCC
OUTLEVEL = LOW
With back termination as shown in Figure 4,
OUTLEVEL = OPEN
Single-ended, OUTLEVEL = HIGH
Single-ended, OUTLEVEL = HIGH
800
VCC -
600
Single-ended
VCC -
10
1000
500
910
VCC
1200
mVP-P
mV
VCC -
400
mV
VCC +
10
mV
2 _______________________________________________________________________________________
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