MAX3544 Просмотр технического описания (PDF) - Maxim Integrated

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MAX3544

Multiband Digital Television Tuner

Maxim Integrated 

Multiband Digital Television Tuner

Pin Description (continued)

PIN

NAME

30

TFVL1* VHF Low Tracking Filter 1

FUNCTION

31

TFVL2* VHF Low Tracking Filter 2

32

TFVH1* VHF High Tracking Filter 1

33

TFVH2* VHF High Tracking Filter 2

34

TFU1* UHF Tracking Filter 1

35

TFU2A* UHF Tracking Filter 2A

36

TFU2B* UHF Tracking Filter 2B

37

TFU3* UHF Tracking Filter 3

38

LEXT* RF VGA Supply Voltage. Connect through a 270nH pullup inductor to VCC.

40

RFINL Low-Frequency RF Input. Matched to 75I over the operating band. Requires a DC-blocking capacitor.

—

EP (GND) Exposed Paddle Ground. Solder evenly to the PCB ground plane for proper operation.

*Improper placement of these inductors degrades image rejection, gain, and noise figure. Copy Maxim reference design layout

exactly in this area.

Detailed Description

I2C-Compatible Serial Interface

The MAX3544 uses a 2-wire I2C-compatible serial inter-

face consisting of a serial data line (SDA) and a serial

clock line (SCL). SDA and SCL facilitate bidirectional

communication between the MAX3544 and the master

at clock frequencies up to 400kHz. The master initiates a

data transfer on the bus and generates the SCL signal to

permit data transfer. The MAX3544 behaves as a slave

device that transfers and receives data to and from the

master. Pull SDA and SCL high with external pullup resis-

tors for proper bus operation.

One bit is transferred during each SCL clock cycle. A

minimum of nine clock cycles is required to transfer a

byte in or out of the MAX3544 (8 data bits and an ACK/

NACK). The data on SDA must remain stable during the

high period of the SCL clock pulse. Changes in SDA

while SCL is high and stable are considered control sig-

nals (see the START and STOP Conditions section). Both

SDA and SCL remain high when the bus is not busy.

START and STOP Conditions

The master initiates a transmission with a START condi-

tion (S), which is a high-to-low transition on SDA while

SCL is high. The master terminates a transmission with a

STOP condition (P), which is a low-to-high transition on

SDA while SCL is high.

Acknowledge and Not-Acknowledge Conditions

Data transfers are framed with an acknowledge bit (ACK)

or a not-acknowledge bit (NACK). Both the master and

the MAX3544 (slave) generate acknowledge bits. To

generate an acknowledge, the receiving device must

pull SDA low before the rising edge of the acknowledge-

related clock pulse (ninth pulse) and keep it low during

the high period of the clock pulse.

To generate a not-acknowledge condition, the receiver

allows SDA to be pulled high before the rising edge

of the acknowledge-related clock pulse, and leaves

SDA high during the high period of the clock pulse.

Monitoring the acknowledge bits allows for detection of

unsuccessful data transfers. An unsuccessful data trans-

fer happens if a receiving device is busy or if a system

fault has occurred. In the event of an unsuccessful data

transfer, the bus master must reattempt communication

at a later time.

Slave Address

The MAX3544 has a 7-bit slave address plus one R/W

bit. These 8 bits must be sent to the device following a

START condition to initiate communication. The slave

address is determined by the state of the ADDR pin as

shown in Table 2.

Table 2. Address Configurations

ADDR PIN

0

Unconnected

1

ADDR2

0

0

1

ADDR1

WRITE AD-

DRESS

READ AD-

DRESS

0

0xC0

0xC1

1

0xC2

0xC3

0

0xC4

0xC5

8   _______________________________________________________________________________________

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