MAX3272 Просмотр технического описания (PDF) - Maxim Integrated

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производитель

MAX3272

+3.3V, 2.5Gbps Low-Power Limiting Amplifiers

Maxim Integrated 

+3.3V, 2.5Gbps Low-Power

Limiting Amplifiers

Interface Schematics

VCC

VCC

0.25pF

IN+

IN-

0.25pF

ESD

STRUCTURES

540Ω

540Ω

110Ω

8kΩ

LOS

GND

Figure 4a. LOS Output Circuit for MAX3272

VCC

ESD

STRUCTURE

GND

Figure 3. Input Circuit

Two control voltages VASSERT, and VDEASSERT, define

the LOS assert and deassert levels. To prevent LOS

chatter in the region of the programmed threshold,

approximately 3.3dB of hysteresis is built into the LOS

assert/deassert function. Once asserted, LOS is not

deasserted until the input amplitude rises to the

required level (VDEASSERT).

To facilitate interfacing with +5V modules, the LOS and

LOS pins on the MAX3272 do not have internal ESD

protection. If ESD protection is desired, a low-capaci-

tance Schottky diode or diode array structure, such as

the MAX3202E, is recommended (see the Typical

Operating Circuits).

The LOS and LOS pins on the MAX3272A include ESD

protection and, as a result, cannot be interfaced with

+5V modules.

Gain Stage

The high-bandwidth gain stage provides approximately

42dB of gain.

8kΩ

LOS

ESD

STRUCTURE

GND

Figure 4b. LOS Output Circuit for MAX3272A

Offset-Correction Loop

Due to the high gain of the amplifier, the MAX3272/

MAX3272A are susceptible to DC offsets in the signal

path. In communications systems using NRZ data with

a 50% duty cycle, pulse-width distortion present in the

signal or generated by the transimpedance amplifier

appears as input offset and is removed by the offset-

cancellation loop. An external capacitor is required

between CAZ1 and CAZ2 to decouple the offset-can-

cellation loop and determine the lower 3dB frequency

of the signal path.

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