MAX31782 Просмотр технического описания (PDF) - Maxim Integrated

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MAX31782

System Management Microcontroller

Maxim Integrated 

System Management Microcontroller

ELECTRICAL CHARACTERISTICS: JTAG INTERFACE

(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted.) (Figure 2)

PARAMETER

JTAG Logic Reference

TCK High Time

TCK Low Time

TCK Low to TDO Output

TMS, TDI Input Setup to TCK

High

TMS, TDI Input Hold after TCK

High

SYMBOL

VREF

tTH

tTL

tTLQ

tDVTH

tTHDX

CONDITIONS

MIN TYP MAX UNITS

VDD/2

V

1

Fs

1

Fs

0.125

Fs

0.30

Fs

0.25

Fs

Note 1: All voltages are referenced to ground (VSS). Currents entering the IC are specified positive and currents exiting the IC are

negative.

Note 2: This value does not include current in SDA, SCL, and P6.0–P6.4.

Note 3: Guaranteed by design.

Note 4: ADCCLK = SYSCLK/16. This is following an initial startup time of approximately 80µs.

Note 5: Base line accuracy of reference source + 0.25% introduced by the MAX31782.

Note 6: The voltage applied to the pins must not exceed their corresponding absolute maximum voltages.

Note 7: ADC has no missing codes.

Note 8: Minimum SCL frequency applies only when in I2C master mode.

Note 9: After this period, the first clock pulse can be generated.

Note 10: T his device internally provides a hold time of at least 25ns for the SDA signal (referenced to the VIHMIN of the SCL signal)

to bridge the undefined region of the falling edge of SCL.

Note 11: CB—Total capacitance of one bus line in pF.

Note 12: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.

SDA

tBUF

tLOW

SCL

tHD:STA

tR

STOP

START

NOTE: TIMING IS REFERENCED TO VILMAX AND VIHMIN.

tHD:DAT

tF

tHIGH

tSU:DAT

Figure 1. I2C-Compatible Bus Timing Diagram

tHD:STA

tSU:STA

REPEATED

START

tSP

tSU:STO

5

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