MAX31782(2010) Просмотр технического описания (PDF) - Maxim Integrated

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MAX31782
(Rev.:2010)

System Management Microcontroller

Maxim Integrated 

System Management Microcontroller

Detailed Description

The MAX31782 incorporates the 16-bit MAXQ20 micro-

controller core with 16 accumulators and 16-level hard-

ware stack. Three memory blocks provide flash applica-

tion code space, utility ROM code space, and RAM mem-

ory. Specialized peripherals are integrated to perform

PWM control of fan speed, read fan tachometers, and

perform temperature monitoring using diode-connected

transistors. The device also features two I2C-compatible

communication peripherals. The slave I2C-compatible

peripheral is included to allow communication between

a host system and the device. An I2C-compatible master

interface is also included to allow communication with

remote I2C digital temperature sensors or other I2C

devices. General-purpose I/O pins (GPIOs) are also

provided to allow interrupt functions and control of other

circuitry using the system management microprocessor.

The MAXQ20 core, along with the specialized peripher-

als, provides a flexible solution for system and thermal

management. Flexibility is further enhanced as the solu-

tion allows for upgrading the program and data flash

contents over the I2C-compatible interface. Updates to

the program flash are protected against unauthorized

writes by a 256-bit user password.

The following sections are an introduction to the primary

features of the MAX31782 system management micro-

controller. More detailed descriptions of the device fea-

tures can be found in the user’s guides described in the

Additional Documentation section.

MAXQ20 Core Architecture

The device employs a MAXQ20 low-cost, high-perfor-

mance, CMOS, fully static, 16-bit RISC microcontroller

with flash memory. It is structured on a highly advanced,

16-accumulator-based, 16-bit RISC architecture. Fetch

and execution operations are completed in one cycle

without pipelining, since the instruction contains both

the op code and data. The highly efficient core is sup-

ported by 16 accumulators and a 16-level hardware

stack, enabling fast subroutine calling and task switch-

ing. Data can be quickly and efficiently manipulated with

three internal data pointers. Multiple data pointers allow

more than one function to access data memory without

having to save and restore data pointers each time. The

data pointers can automatically increment or decrement

following an operation, eliminating the need for software

intervention.

Instruction Set

The instruction set is composed of fixed-length, 16-bit

instructions that operate on registers and memory loca-

tions. The instruction set is highly orthogonal, allowing

arithmetic and logical operations to use any register

along with the accumulator. Special-function registers

control the peripherals and are subdivided into register

modules. The family architecture is modular, so that new

devices and modules can reuse code developed for

existing products.

The architecture is transport-triggered. This means that

writes or reads from certain register locations can also

cause side effects to occur. These side effects form the

basis for higher level op codes defined by the assembly,

such as ADDC, OR, JUMP, etc. The op codes are imple-

mented as MOVE instructions between certain register

locations, while the assembler handles the encoding,

which need not be a concern to the programmer. The

16-bit instruction word is designed for efficient execution.

Bit 15 indicates the format for the source field of the

instruction. Bits 0–7 of the instruction represent the

source for the transfer. Depending on the value of the

format field, this can either be an immediate value or

a source register. If this field represents a register, the

lower 4 bits contain the module specifier and the upper

4 bits contain the register index in that module.

Bits 8–14 represent the destination for the transfer. This

value always represents a destination register, with the

lower 4 bits containing the module specifier and the

upper 3 bits containing the register subindex within that

module. Any time it is necessary to directly select one of

the upper 24 registers as a destination, the prefix regis-

ter, PFX, is needed to supply the extra destination bits.

This prefix register write is inserted automatically by the

assembler and requires only one additional execution

cycle. Refer to the MAXQ Family User’s Guide for com-

plete instruction set information.

Memory Organization

The device incorporates several memory areas, including:

• 32KWords of flash memory for application program

storage

• 1KWords of SRAM for storage of temporary variables

• 4KWords of utility ROM contain a debugger and pro-

gram loader

• 16-level stack memory for storage of program return

addresses and general-purpose use

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