MAX19707ETM Просмотр технического описания (PDF) - Maxim Integrated
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MAX19707ETM Datasheet PDF : 37 Pages
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10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
VDD Supply Current
OVDD Supply Current
Standby mode: CLK = 0 or OVDD;
aux-DACs ON and at midscale,
aux-ADC ON
Idle mode: fCLK = 45MHz; aux-DACs ON
and at midscale, aux-ADC ON
Shutdown mode: CLK = 0 or OVDD
Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx,
SPI1-Rx, SPI3-Rx states; receive ADC
operating mode (Rx): fCLK = 45MHz,
fIN = 5.5MHz on both channels;
aux-DACs ON and at midscale,
aux-ADC ON
Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx,
SPI2-Tx, SPI4-Tx states; transmit DAC
operating mode (Tx), fCLK = 45MHz, fOUT
= 2.2MHz on both channels; aux-DACs
ON and at midscale, aux-ADC ON
3.2
5
mA
12.1
15
1
µA
7.7
mA
485
µA
Rx ADC DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
DC Gain Matching
Offset Matching
Gain Temperature Coefficient
Power-Supply Rejection
Standby mode: CLK = 0 or OVDD; aux-DACs
1
ON and at midscale, aux-ADC ON
Idle mode: fCLK = 45MHz; aux-DACs ON
76
and at midscale, aux-ADC ON
Shutdown mode: CLK = 0 or OVDD
1
N
INL
DNL
Residual DC offset error
Include reference error
PSRR
Offset error (VDD ±5%)
Gain error (VDD ±5%)
-5
-5.5
-0.15
10
±1.6
±0.7
±0.5
±1.0
±0.01
±13
±30
±0.4
±0.1
+5
+5.5
+0.15
Bits
LSB
LSB
%FS
%FS
dB
LSB
ppm/°C
LSB
%FS
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