M5M5W816TP-70HI Просмотр технического описания (PDF) - Renesas Electronics
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M5M5W816TP-70HI Datasheet PDF : 10 Pages
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2002.08.30 Ver. 6.1
M5M5W816TP - 55HI, 70HI, 85HI
MITSUBISHI LSIs
(4)TIMING DIAGRAMS
Read cycle
A 0~18
BC1#,BC2#
(Note3)
S#
(Note3)
OE#
W# = "H" lev el
DQ1~16
(Note3)
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
tCR
ta(A)
ta(BC1) or ta(BC2)
ta(S)
ta (OE)
ten (OE)
ten (BC1)
ten (BC2)
ten (S)
tv (A)
tdis (BC1) or tdis (BC2)
tdis (S)
tdis (OE)
VALID DATA
(Note3)
(Note3)
(Note3)
Write cycle ( W# control mode )
tCW
A 0~18
BC1#,BC2#
S#
(Note3)
(Note3)
tsu (BC1) or tsu(BC2)
tsu (S)
OE#
W#
DQ1~16
tsu (A)
tsu (A-WH)
tw (W)
tdis (W)
tdis(OE)
DATA IN
STABLE
tsu (D) th (D)
trec (W)
ten(OE)
ten (W)
(Note3)
(Note3)
5
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