M48T212A-85MH1 Просмотр технического описания (PDF) - STMicroelectronics
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M48T212A-85MH1 Datasheet PDF : 20 Pages
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M48T212A
Table 13. TIMEKEEPER Register Map
Address
Fh
Eh
Dh
Ch
Bh
Ah
9h
8h
7h
6h
5h
4h
3h
2h
1h
0h
D7
0
0
0
0
0
ST
W
WDS
AFE
RPT4
RPT3
RPT2
RPT1
WDF
D6
D5
D4
10 Years
0
0
10M
0
10 Date
FT
0
0
0
10 Hours
10 Minutes
10 Seconds
R
S
BMB4 BMB3 BMB2
0
ABE Al 10M
RPT5
AI 10 Date
0
AI 10 Hour
Alarm 10 Minutes
Alarm 10 Seconds
1000 Year
AF
Y
BL
D3
D2
D1
D0
Year
Month
Date: Day of Month
0
Day of Week
Hours (24 Hour Format)
Minutes
Seconds
Calibration
BMB1 BMB0 RB1
RB0
Alarm Month
Alarm Date
Alarm Hour
Alarm Minutes
Alarm Seconds
100 Year
Y
Y
Y
Y
Function/Range
BCD Format
Year
Month
Date
Day
Hour
Min
Sec
Control
Watchdog
A Month
A Date
A Hour
A Min
A Sec
Century
Flag
00-99
01-12
01-31
01-7
00-23
00-59
00-59
01-12
01-31
00-23
00-59
00-59
00-99
Keys:
S = Sign Bit
FT = Frequency Test Bit
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag
BMB0-BMB4 = Watchdog Multiplier Bits
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag
AF = Alarm flag
Y = ’1’ or ’0’
The RST signal also remains active during this
time (see Figure 5).
Note: Most low power SRAMs on the market to-
day can be used with the M48T212A TIMEKEEP-
ER Controller. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all oth-
er inputs to the SRAM. This allows inputs to the
M48T212A and SRAMs to be Don’t Care once
VCC falls below VPFD(min). The SRAM should also
guarantee data retention down to VCC = 2.0V. The
chip enable access time must be sufficient to meet
the system needs with the chip enable output
propagation delays included.
If the SRAM includes a second chip enable pin
(E2), this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use.
The data retention current value of the SRAMs can
then be added to the IBAT value of the M48T212A
to determine the total current requirements for
data retention. The available battery capacity can
then be divided by this current to determine the
amount of data retention available.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
11/20
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