M48T212A-85MH1 Просмотр технического описания (PDF) - STMicroelectronics
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M48T212A-85MH1 Datasheet PDF : 20 Pages
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M48T212A
Table 12. Alarm Repeat Modes
RPT5
RPT4
RPT3
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
RPT2
1
1
0
0
0
0
Figure 9. Alarm Interrupt Reset Waveforms
RPT1
1
0
0
0
0
0
A0-A3
1h
ADDRESS 0h
Alarm Setting
Once per Second
Once per Minute
Once per Hour
Once per Day
Once per Month
Once per Year
Fh
ACTIVE FLAG BIT
IRQ/FT
HIGH-Z
AI03021
WRITE MODE
The M48T212A is in the Write Mode whenever W
(Write Enable) and E (Chip Enable) are in a low
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W or E. A write is terminated by the
earlier rising edge of W or E. The addresses must
be held valid throughout the cycle. E or W must re-
turn high for a minimum of tEHAX from Chip Enable
or tWHAX from Write Enable prior to the initiation of
another read or write cycle. Data-in must be valid
tDVWH prior to the end of write and remain valid for
tWHDX afterward.
G should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs tWLQZ after W falls.
When E is low during the write, one of the on-
board TIMEKEEPER registers will be selected and
data will be written into the device. When EX is low
(and E is high) an external SRAM location is se-
lected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
DATA RETENTION MODE
With valid VCC applied, the M48T212A can be ac-
cessed as described above with read or write cy-
cles. Should the supply voltage decay, the
M48T212A will automatically deselect, write pro-
tecting itself (and any external SRAM) when VCC
falls between VPFD (max) and VPFD (min). This is
accomplished by internally inhibiting access to the
clock registers via the E signal. At this time, the
Reset pin (RST) is driven active and will remain
active until VCC returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing E1CON and E2CON to a high level.
This level is within 0.2V of the VBAT. E1CON and
E2CON will remain at this level as long as VCC re-
mains at an out-of tolerance condition.
When VCC falls below the level of the battery
(VBAT), power input is switched from the VCC pin
to the battery and the clock registers and external
SRAM are maintained from the attached battery
supply. All outputs become high impedance. The
VOUT pin is capable of supplying 100µA of current
to the attached memory with less than 0.3V drop
under this condition. On power up, when VCC re-
turns to a nominal value, write protection contin-
ues for 200ms (max) by inhibiting E1CON or
E2CON.
10/20
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