M40Z111WMH1TR Просмотр технического описания (PDF) - STMicroelectronics

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M40Z111WMH1TR

NVRAM CONTROLLER for up to TWO LPSRAM

STMicroelectronics 

M40Z111, M40Z111W

Table 3. AC Measurement Condition

Input Rise and Fall Times

≤ 5ns

Input Pulse Voltages

0 to 3V

Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no

longer driven.

Manufacturers generally specify a typical condition

for room temperature along with a worst case

condition (generally at elevated temperatures). The

system level requirements will determine the

choice of which value to use. The data retention

current value of the SRAMs can then be added to

the ICCDR value of the M40Z111/111W to determine

the total current requirements for data retention.

The available battery capacity for the SNAPHAT of

your choice can then be divided by this current to

determine the amount of data retention available

(see Table 7). For more information on Battery

Storage Life refer to the Application Note AN1012.

VCC NOISE AND NEGATIVE-GOING TRAN-

SIENTS

ICC transients, including those produced by output

switching, can produce voltage fluctuations, result-

ing in spikes on the VCC bus. These transients can

be reduced if capacitors are used to store energy,

which stabilizes the VCC bus. The energy stored in

the bypass capacitors will be released as low going

spikes are generated or energy will be absorbed

when overshoots occur.

Figure 4. AC Testing Load Circuit

DEVICE

UNDER

TEST

645Ω

CL = 100pF

or 5pF

1.75V

CL includes JIG capacitance

AI02326

A ceramic bypass capacitor value of 0.1µF (as

shown in Figure 4) is recommended in order to

provide the needed filtering. In addition to tran-

sients that are caused by normal SRAM operation,

power cycling can generate negative voltage

spikes on VCC that drive it to values below VSS by

as much as one volt. These negative spikes can

cause data corruption in the SRAM while in battery

backup mode. To protect from these voltage

spikes, ST recommends connecting a schottky di-

ode from VCC to VSS (cathode connected to VCC,

anode to VSS).

Table 4. Capacitance (1)

(TA = 25°C; f = 1MHz)

Symbol

Parameter

CIN

Input Capacitance

COUT (2)

Output Capacitance

Note: 1. Sampled only, not 100% tested.

2. Outputs deselected.

Test Condition

Min

Max

Unit

VIN = 0V

8

pF

VOUT = 0V

10

pF

4/12

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