M40Z111WMH1TR Просмотр технического описания (PDF) - STMicroelectronics

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M40Z111WMH1TR

NVRAM CONTROLLER for up to TWO LPSRAM

STMicroelectronics 

Figure 3. Hardware Hookup

M40Z111, M40Z111W

3.3V or 5V

1N5817 or

MBR5120T3

0.1µF

Thereshold

VCC

VOUT

E

THS

VSS

M40Z111

ECON

VCC

0.1µF

CMOS

SRAM

E

x8 or x16

AI02394

When VCC degrades during a power failure,ECON

is forced inactive independent of E. In this situation,

the SRAM is unconditionally write protected as VCC

falls below an out-of-tolerance threshold (VPFD).

The power fail detection value associated with VPFD

is selected by the THS pin and is shown in Table 5.

(Note: THS pin must be connected to either VSS or

VOUT). If chip enable access is in progress during

a power fail detection, that memory cycle continues

to completion before the memory is write protected.

If the memory cycle is not terminated within time

tWP, ECON is unconditionally driven high, write pro-

tecting the SRAM.

A power failure during a write cycle may corrupt

data at the currently addressed location, but does

not jeopardize the rest of the SRAM’s contents. At

voltages below VPFD (min), the user can be assured

the memory will be write protected provided the

VCC fall time exceeds tF.

As VCC continues to degrade, the internal switch

disconnects VCC and connects the internal battery

to VOUT. This occurs at the switchover voltage

(VSO). Below the VSO, the battery provides a volt-

age VOHB to the SRAM and can supply current

IOUT2 (see Table 5). When VCC rises above VSO,

VOUT is switched back to the supply voltage. Output

ECON is held inactive for tER (200ms maximum)

after the power supply has reached VPFD, inde-

pendent of the E input, to allow for processor

stabilization (see Figure 6).

DATA RETENTION LIFETIME CALCULATION

Most low power SRAMs on the market today can

be used with the M40Z111/111W NVRAM Control-

ler. There are, however some criteria which should

be used in making the final choice of which SRAM

to use. The SRAM must be designed in a way

where the chip enable input disables all other in-

puts to the SRAM. This allows inputs to the

M40Z111/111W and SRAMs to be Don’t Care once

VCC falls below VPFD (min). The SRAM should also

guarantee data retention down to VCC =2.0V. The

chip enable access time must be sufficient to meet

the system needs with the chip enable propagation

delays included. If the SRAM includes a second

chip enable pin (E2), this pin should be tied to VOUT.

If data retention lifetime is a critical parameter for

the system, it is important to review the data reten-

tion current specifications for the particular SRAMs

being evaluated. Most SRAMs specify a data re-

tention current at 3.0V.

3/12

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