M40Z111MH1TR Просмотр технического описания (PDF) - STMicroelectronics

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M40Z111MH1TR

NVRAM CONTROLLER for up to TWO LPSRAM

STMicroelectronics 

M40Z111, M40Z111W

Table 2. Absolute Maximum Ratings (1)

Symbol

Parameter

Value

Unit

TA

Ambient Operating Temperature

0 to 70

°C

TSTG

Storage Temperature (VCC Off) SNAPHAT

SOIC

–40 to 85

–55 to 125

°C

TSLD (2)

Lead Solder Temperature for 10 seconds

260

°C

VIO

Input or Output Voltages

VCC

Supply Voltage

IO

Output Current

–0.3 to VCC +0.3

V

–0.3 to 7

V

20

mA

PD

Power Dissipation

1

W

Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may

affect reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.

CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Figure 2. SOIC Pin Connections

VOUT

NC

NC

NC

NC

VCC

NC

VCC

NC

NC

NC

NC

THS

VSS

1

28

2

27

3

26

4

25

5

24

6

23

7 M40Z111 22

8 M40Z111W 21

9

20

10

19

11

18

12

17

13

16

14

15

AI02239B

VCC

E

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

ECON

NC

Warning: NC = Not Connected.

DESCRIPTION (cont’d)

When an invalid VCC condition occurs, the condi-

tioned chip enable (ECON) output is forced inactive

to write-protect the stored data in the SRAM.

During a power failure, the SRAM is switched from

the VCC pin to the lithium cell within the SNAPHAT

to provide the energy required for data retention.

On a subsequent power-up, the SRAM remains

write protected until a valid power condition returns.

The 28 pin 330mil SOIC provides sockets with gold

plated contacts at both ends for direct connection

to a separate SNAPHAT housing containing the

battery. The unique design allows the SNAPHAT

battery package to be mounted on top of the SOIC

package after the completion of the surface mount

process. Insertion of the SNAPHAT housing after

reflow prevents potential battery damage due to the

high temperatures required for device surface-

mounting. The SNAPHAT housing is keyed to pre-

vent reverse insertion. The SOIC and battery

packages are shipped separately in plastic anti-

static tubes or in Tape & Reel form. For the 28 lead

SOIC, the battery package (i.e. SNAPHAT) part

number is "M4Z28-BR00SH1" or "M4Z32-

BR00SH1" (See Table 7).

OPERATION

The M40Z111/111W, as shown in Figure 4, can

control up to two standard low-power SRAMs.

These SRAMs must be configured to have the chip

enable input disable all other input signals. Most

slow, low-power SRAMs are configured like this,

however many fast SRAMs are not. During normal

operating conditions, the conditioned chip enable

(ECON) output pin follows the chip enable (E) input

pin with timing shown in Table 6. An internal switch

connects VCC to VOUT. This switch has a voltage

drop of less than 0.3V (IOUT1).

2/12

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