AD7849AN Просмотр технического описания (PDF) - Analog Devices

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AD7849AN

Serial Input, 14-Bit/16-Bit DAC

Analog Devices 

AD7849

SCLK

t2

SYNC

t1

t3

BIN/COMP

SDIN

(AD7849B/C/T)

DB15

SDIN

(AD7849A)

DB13

t4

t5

t4

t5

DB0

LDAC, CLR

DCEN IS TIED PERMANENTLY LOW

DB0

t7

Figure 12. Timing Diagram (Stand-Alone Mode)

DIGITAL INTERFACE

The AD7849 contains an input serial to parallel shift register

and a DAC latch. A simplified diagram of the input loading

circuitry is shown in Figure 12. Serial data on the SDIN input

is loaded to the input register under control of DCEN, SYNC

and SCLK. When a complete word is held in the shift register it

may then be loaded into the DAC latch under control of

LDAC. Only the data in the DAC latch determines the analog

output on the AD7849.

The DCEN (daisy-chain enable) input is used to select either a

stand-alone mode or a daisy-chain mode. The loading format is

slightly different depending on which mode is selected.

Serial Data Loading Format (Stand-Alone Mode)

With DCEN at Logic 0 the stand-alone mode is selected. In this

mode a low SYNC input provides the frame synchronization

signal which tells the AD7849 that valid serial data on the SDIN

input will be available for the next 16 falling edges of SCLK. An

internal counter/decoder circuit provides a low gating signal so

that only 16 data bits are clocked into the input shift register.

After 16 SCLK pulses the internal gating signal goes inactive

(high) thus locking out any further clock pulses. Therefore ei-

ther a continuous clock or a burst clock source may be used to

clock in the data.

The SYNC input is taken high after the complete 16-bit word is

loaded in.

The AD7849B, AD7849C and AD7849T versions are 16-bit

resolution DACS and have a straight 16-bit load format, with

the MSB (DB15) being loaded first. The AD7849A is a 14-bit

DAC but the loading structure is still 16-bit. The MSB (DB13)

is loaded first and the final two bits of the 16-bit stream must

be 0s.

There are two ways in which the DAC latch and hence the ana-

log output may be updated. The status of the LDAC input is

examined after SYNC is taken low. Depending on its status,

one of two update modes is selected.

If LDAC = 0 then the automatic update mode is selected. In

this mode the DAC latch and analog output are updated auto-

matically when the last bit in the serial data stream is clocked

in. The update thus takes place on the sixteenth falling SCLK

edge.

If LDAC = 1 then the automatic update is disabled. The DAC

latch update and output update are now separate. The DAC

latch is updated on the falling edge of LDAC. However, the

output update is delayed for a further 5 µs by means of an inter-

nal track-and-hold amplifier in the output stage. This function

results in lower digital-to-analog glitch impulse at the DAC

output. Note that the LDAC input must be taken back high

again before the next data transfer is initiated.

DCEN

SYNC

SCLK

SDIN

LDAC

CLR

RESET EN

÷16

COUNTER/

DECODER

GATED

SIGNAL

GATED

SCLK

INPUT

SHIFT REGISTER

(16 BITS)

AUTO-UPDATE

CIRCUITRY

DAC LATCH

(14/16 BITS)

SDOUT

Figure 13. Simplified Loading Structure

REV. B

–9–

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