HMS30C7202N Просмотр технического описания (PDF) - MagnaChip Semiconductor
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HMS30C7202N Datasheet PDF : 179 Pages
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HMS30C7202N
9.1.2.2 ASR ........................................................................................................................................................ 65
9.1.2.3 TNR0...................................................................................................................................................... 65
9.1.2.4 TSR......................................................................................................................................................... 65
9.1.2.5 CCR0...................................................................................................................................................... 65
9.1.2.6 ADR1 ..................................................................................................................................................... 66
9.1.2.7 TNR1...................................................................................................................................................... 66
9.1.2.8 CCR1...................................................................................................................................................... 66
9.1.2.9 ADR2 ..................................................................................................................................................... 66
9.1.2.10 TNR2 .................................................................................................................................................. 66
9.1.2.11 CCR2 .................................................................................................................................................. 67
9.1.2.12 FLAGR............................................................................................................................................... 67
9.1.2.13 DMAOR ............................................................................................................................................. 67
9.1.3 DMAC operation ........................................................................................................................................ 68
9.2 MMC/ SPI CONTROLLER..................................................................................................................................... 69
9.2.1 External Signals.......................................................................................................................................... 69
9.2.2 Registers (SPI Mode).................................................................................................................................. 69
9.2.2.1 SPIMMC Control Register (SPICR)....................................................................................................... 69
9.2.2.2 SPIMMC Status Register (SPISR).......................................................................................................... 70
9.2.2.3 SPIMMC XCH Counter Register (XCHCNT) ....................................................................................... 70
9.2.2.4 SPIMMC TX Data Buffer Register (TXBUFF)...................................................................................... 70
9.2.2.5 SPIMMC RX Data Buffer Register (RXBUFF) ..................................................................................... 70
9.2.2.6 SPIMMC Reset Register (ResetReg)...................................................................................................... 71
9.2.3 Timings ....................................................................................................................................................... 71
9.2.4 SPI Operation for MMC ............................................................................................................................. 72
9.2.5 Multimedia Card Host Controller............................................................................................................... 73
9.2.6 Registers ..................................................................................................................................................... 73
9.2.6.1 MMC Mode Register.............................................................................................................................. 73
9.2.6.2 MMC Operation Register ....................................................................................................................... 74
9.2.6.3 MMC Status Register ............................................................................................................................. 74
9.2.6.4 MMC Interrupt Enable Register ............................................................................................................. 75
9.2.6.5 MMC Block Size Register...................................................................................................................... 76
9.2.6.6 MMC Block Number Register................................................................................................................ 76
9.2.6.7 MMC Time Period Register.................................................................................................................... 76
9.2.6.8 MMC Command Buffer Register ........................................................................................................... 76
9.2.6.9 MMC Argument Buffer Register ............................................................................................................ 76
9.2.6.10 MMC Response Buffer Register......................................................................................................... 77
9.2.6.11 MMC Data Buffer Register ................................................................................................................ 77
9.2.6.12 MMC Ready Timeout Register........................................................................................................... 77
9.2.7 Basic Operation in MMC Mode.................................................................................................................. 77
9.2.7.1 Write Operation ...................................................................................................................................... 78
9.2.7.2 Read Operation....................................................................................................................................... 78
9.3 SMC CONTROLLER.............................................................................................................................................. 79
9.3.1 External Signals.......................................................................................................................................... 79
9.3.2 Registers ..................................................................................................................................................... 79
9.3.2.1 SMC Command Register (SMCCMD) ................................................................................................... 79
9.3.2.2 SMC Address Register (SMCADR) ....................................................................................................... 80
9.3.2.3 SMC Data Write Register (SMCDATW)................................................................................................ 80
9.3.2.4 SMC Data Read Register (SMCDATR).................................................................................................. 81
9.3.2.5 SMC Configuration Register (SMCCONF)............................................................................................ 81
9.3.2.6 SMC Timing Parameter Register (SMCTIME) ...................................................................................... 82
9.3.2.7 SMC Status Register (SMCSTAT).......................................................................................................... 82
9.4 SOUND INTERFACE............................................................................................................................................... 84
9.4.1 External Signals.......................................................................................................................................... 84
9.4.2 Registers ..................................................................................................................................................... 84
9.4.2.1 SCONT................................................................................................................................................... 84
9.4.2.2 SDADR .................................................................................................................................................. 85
9.5 USB SLAVE INTERFACE ....................................................................................................................................... 86
9.5.1 Block Diagram ........................................................................................................................................... 87
9.5.2 Theory of Operation ................................................................................................................................... 87
9.5.3 Endpoint FIFOs (Rx, Tx) ............................................................................................................................ 90
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