HMS30C7202N Просмотр технического описания (PDF) - MagnaChip Semiconductor
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HMS30C7202N Datasheet PDF : 179 Pages
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HMS30C7202N
5.4.1
5.4.2
5.4.3
Reset Sequences of Power On Reset........................................................................................................... 34
Software Generated Warm Reset ................................................................................................................ 35
An Externally generated Warm Reset ......................................................................................................... 35
6 SDRAM CONTROLLER........................................................................................................................................ 37
6.1 SUPPORTED MEMORY DEVICES ............................................................................................................................ 37
6.2 REGISTERS .......................................................................................................................................................... 38
6.2.1 SDRAM Controller Configuration Register (SDCON) ............................................................................... 38
6.2.2 SDRAM Controller Refresh Timer Register (SDREF) ................................................................................ 40
6.2.3 SDRAM Controller Write buffer flush timer Register (SDWBF)................................................................. 40
6.2.4 SDRAM Controller Wait Driver Register (SDWAIT) .................................................................................. 40
6.3 POWER-UP INITIALIZATION OF THE SDRAMS....................................................................................................... 40
6.4 SDRAM MEMORY MAP ...................................................................................................................................... 41
6.5 AMBA ACCESSES AND ARBITRATION .................................................................................................................. 42
6.6 MERGING WRITE BUFFER .................................................................................................................................... 42
7 STATIC MEMORY INTERFACE.......................................................................................................................... 44
7.1 EXTERNAL SIGNALS............................................................................................................................................. 44
7.2 FUNCTIONAL DESCRIPTION .................................................................................................................................. 44
7.2.1 Memory bank select.................................................................................................................................... 44
7.2.2 Access sequencing ...................................................................................................................................... 44
7.2.3 Wait states generation ................................................................................................................................ 45
7.2.4 Burst read control....................................................................................................................................... 45
7.2.5 Byte lane write control ............................................................................................................................... 45
7.3 REGISTERS .......................................................................................................................................................... 46
7.3.1 MEM Configuration Register ..................................................................................................................... 46
7.4 EXAMPLES OF THE SMI READ, WRITE WAIT TIMING DIAGRAM .............................................................................. 47
7.4.1 Read normal wait (Non-Sequential mode).................................................................................................. 47
7.4.2 Read normal wait (Sequential mode) ......................................................................................................... 48
7.4.3 Read burst wait (Sequential mode)............................................................................................................. 49
7.4.4 Write normal wait (Sequential mode) ......................................................................................................... 50
7.5 INTERNAL SRAM ................................................................................................................................................ 51
7.5.1 Remapping Enable Register ....................................................................................................................... 51
7.5.2 Remap Source Address Register ................................................................................................................. 51
8 LCD CONTROLLER .............................................................................................................................................. 52
8.1 VIDEO OPERATION ............................................................................................................................................... 52
8.1.1 LCD datapath............................................................................................................................................. 53
8.1.1.1 Palette RAM & 16bpp mode .................................................................................................................. 53
8.1.2 Color/Grayscale Dithering......................................................................................................................... 55
8.1.3 How to order the bit on LD[7:0] output ..................................................................................................... 55
8.1.4 TFT mode ................................................................................................................................................... 56
8.2 REGISTERS .......................................................................................................................................................... 56
8.2.1 LCD Power Control ................................................................................................................................... 56
8.2.2 LCD Controller Status/Mask and Interrupt Registers ................................................................................ 57
8.2.3 LCD DMA Base Address Register .............................................................................................................. 58
8.2.4 LCD DMA Channel Current Address Register ........................................................................................... 58
8.2.5 LCD Timing 0 Register............................................................................................................................... 58
8.2.6 LCD Timing 1 Register............................................................................................................................... 59
8.2.7 LCD Timing 2 Register............................................................................................................................... 60
8.2.8 LCD Test Register....................................................................................................................................... 61
8.2.9 Grayscaler Test Registers ........................................................................................................................... 61
8.2.10 LCD Palette registers ................................................................................................................................. 62
8.3 TIMINGS .............................................................................................................................................................. 63
9 FAST AMBA PERIPHERALS ................................................................................................................................ 64
9.1 DMA CONTROLLER............................................................................................................................................. 64
9.1.1 External Signals ......................................................................................................................................... 64
9.1.2 Registers..................................................................................................................................................... 64
9.1.2.1 ADR0 ..................................................................................................................................................... 65
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